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Energy aware and reliable STT-RAM based cache design for 3D embedded chip-multiprocessors.

Fatemeh ArezoomandArghavan AsadMahdi FazeliMahmood FathyFarah Mohammadi
Published in: ReCoSoC (2017)
Keyphrases
  • energy aware
  • single chip
  • low cost
  • high speed
  • embedded systems
  • multithreading
  • memory subsystem
  • user interface
  • data center
  • fault tolerant
  • high performance computing