Testing CMOS combinational iterative logic arrays for realistic faults.
Dimitris GizopoulosDimitris NikolosAntonis M. PaschalisPublished in: Integr. (1996)
Keyphrases
- asynchronous circuits
- delay insensitive
- test cases
- fault model
- logic circuits
- random access memory
- built in self test
- focal plane
- logic programming
- predicate logic
- real world
- chip design
- fault diagnosis
- modal logic
- real life
- high speed
- classical logic
- software testing
- software development
- test sequences
- fault detection
- power consumption
- logical framework
- circuit design
- test generation
- multi valued
- error correction
- low power
- low voltage
- analog vlsi
- low cost