Unai Bidarte

Publication Activity (10 Years)

Years Active: 2003-2023
Publications (10 Years): 15

Top Topics

Certainty Factor

Production System

Top Venues

Comput. Electr. Eng.

Reliab. Eng. Syst. Saf.

Publications

Sara Alonso, Jesús Lázaro, Jaime Jiménez, Leire Muguira, Unai Bidarte
Timing requirements on multi-processing and reconfigurable embedded systems with multiple environments. DCIS (2023)
Sara Alonso, Jesús Lázaro, Jaime Jiménez, Leire Muguira, Unai Bidarte
The influence of virtualization on real-time systems' interrupts in embedded SoC platforms. DCIS (2022)
Jesús Lázaro, Unai Bidarte, Leire Muguira, Armando Astarloa, Jaime Jiménez
Embedded firewall for on-chip bus transactions. Comput. Electr. Eng. 98 (2022)
Sara Alonso, Jesús Lázaro, Jaime Jimenez, Leire Muguira, Unai Bidarte
Evaluating the OpenAMP framework in real-time embedded SoC platforms. DCIS (2021)
Jesús Lázaro, Unai Bidarte, Leire Muguira, Carlos Cuadrado, Jaime Jiménez
Fast and efficient address search in System-on-a-Programmable-Chip using binary trees. Comput. Electr. Eng. 96 (Part) (2021)
Mikel Rodriguez, Jesús Lázaro, Unai Bidarte, Jaime Jiménez, Armando Astarloa
A Fixed-Latency Architecture to Secure GOOSE and Sampled Value Messages in Substation Systems. IEEE Access 9 (2021)
Carlos Cuadrado, Iñigo Kortabarria, Jesús Lázaro, Unai Bidarte, Jaime Jiménez
Fast and efficient FPGA prototype system for embedded control algorithms in electric traction. DCIS (2019)
Marcelo Urbina, Tatiana Acosta, Jesús Lázaro, Armando Astarloa, Unai Bidarte
Smart Sensor: SoC Architecture for the Industrial Internet of Things. IEEE Internet Things J. 6 (4) (2019)
Igor Villalta, Unai Bidarte, Julen Gomez-Cornejo, Jaime Jimenez, Jesús Lázaro
SEU emulation in industrial SoCs combining microprocessor and FPGA. Reliab. Eng. Syst. Saf. 170 (2018)
Mikel Rodriguez, Armando Astarloa, Jesús Lázaro, Unai Bidarte, Jaime Jimenez
System-on-Programmable-Chip AES-GCM implementation for wire-speed cryptography for SAS. DCIS (2018)
Marcelo Urbina, Armando Astarloa, Jesús Lázaro, Unai Bidarte, Igor Villalta, Mikel Rodriguez
Cyber-Physical Production System Gateway Based on a Programmable SoC Platform. IEEE Access 5 (2017)
Igor Villalta, Unai Bidarte, Julen Gomez-Cornejo, Jesús Lázaro, Armando Astarloa
Estimating the SEU failure rate of designs implemented in FPGAs in presence of MCUs. Microelectron. Reliab. 78 (2017)
Naiara Moreira, Jesús Lázaro, Unai Bidarte, Jaime Jimenez, Armando Astarloa
On the Utilization of System-on-Chip Platforms to Achieve Nanosecond Synchronization Accuracies in Substation Automation Systems. IEEE Trans. Smart Grid 8 (4) (2017)
Armando Astarloa, Unai Bidarte, Jaime Jimenez, Aitzol Zuloaga, Jesús Lázaro
Intelligent gateway for Industry 4.0-compliant production. IECON (2016)
Uli Kretzschmar, Julen Gomez-Cornejo, Armando Astarloa, Unai Bidarte, Javier Del Ser
Synchronization of faulty processors in coarse-grained TMR protected partially reconfigurable FPGA designs. Reliab. Eng. Syst. Saf. 151 (2016)
Armando Astarloa, Naiara Moreira, Unai Bidarte, Marcelo Urbina, David Modrono
FPGA based nodes for sub-microsecond synchronization of cyber-physical production systems on high availability ring networks. ReConFig (2015)
Igor Villata, Unai Bidarte, Uli Kretzschmar, Armando Astarloa, Jesús Lázaro
Fast and accurate SEU-tolerance characterization method for Zynq SoCs. FPL (2014)
Julen Gomez-Cornejo, Aitzol Zuloaga, Uli Kretzschmar, Unai Bidarte, Jaime Jimenez
Fast context reloading lockstep approach for SEUs mitigation in a FPGA soft core processor. IECON (2013)
Armando Astarloa, Jesús Lázaro, Unai Bidarte, Aitzol Zuloaga, Mikel Idirin
System-on-Chip implementation of Reliable Ethernet Networks nodes. IECON (2013)
Jesús Lázaro, Armando Astarloa, Aitzol Zuloaga, Unai Bidarte, Jaime Jimenez
I2CSec: A secure serial Chip-to-Chip communication protocol. J. Syst. Archit. 57 (2) (2011)
Uli Kretzschmar, Armando Astarloa, Jesús Lázaro, Unai Bidarte, Jaime Jimenez
Robustness Analysis of Different AES Implementations on SRAM Based FPGAs. ReConFig (2011)
Taho Dorta, Jaime Jimenez, José Luis Martín, Unai Bidarte, Armando Astarloa
Reconfigurable Multiprocessor Systems: A Review. Int. J. Reconfigurable Comput. 2010 (2010)
Armando Astarloa, Jesús Lázaro, Unai Bidarte, Aitzol Zuloaga, José Luis Martín
An Autonomous Fault Tolerant System for CAN Communications. IEA/AIE (3) (2010)
Jesús Lázaro, Armando Astarloa, Unai Bidarte, Jaime Jimenez, Aitzol Zuloaga
AES-Galois Counter Mode Encryption/Decryption FPGA Core for Industrial and Residential Gigabit Ethernet Communications. ARC (2009)
Armando Astarloa, Jesús Lázaro, Unai Bidarte, Aitzol Zuloaga, Jaime Jimenez
PCIREX: A Fast Prototyping Platform for TMR Dynamically Reconfigurable Systems. ReConFig (2009)
Armando Astarloa, Jesús Lázaro, Unai Bidarte, Aitzol Zuloaga, Jaime Jimenez
DNAX-BCU: An Un-clonable Cost-conscious SoPC Implementation for Bus Coupling Units of the European Installation Bus. ICDCS Workshops (2009)
Taho Dorta, Jaime Jimenez, José Luis Martín, Unai Bidarte, Armando Astarloa
Overview of FPGA-Based Multiprocessor Systems. ReConFig (2009)
Armando Astarloa, Unai Bidarte, Jesús Lázaro, Jon Andreu, José Luis Martín
Configurable-System-on-Programmable-Chip for Power Electronics Control Applications. ReConFig (2008)
Armando Astarloa, Unai Bidarte, Jaime Jimenez, Jesús Lázaro, Iñigo Martínez de Alegría
Secure Ethernet Point-to-Point Links for Autonomous Electronic Ballot Boxes. ATC (2008)
Armando Astarloa, Aitzol Zuloaga, Unai Bidarte, José Luis Martín, Jesús Lázaro, Jaime Jimenez
Tornado: A self-reconfiguration control system for core-based multiprocessor CSoPCs. J. Syst. Archit. 53 (9) (2007)
Jesús Lázaro, Jagoba Arias, Armando Astarloa, Unai Bidarte, Aitzol Zuloaga
Hardware architecture for a general regression neural network coprocessor. Neurocomputing 71 (1-3) (2007)
Jaime Jimenez, José Luis Martín, Unai Bidarte, Armando Astarloa, Aitzol Zuloaga
Design of a Master Device for the Multifunction Vehicle Bus. IEEE Trans. Veh. Technol. 56 (6) (2007)
Jaime Jimenez, José Luis Martín, Aitzol Zuloaga, Unai Bidarte, Jagoba Arias
Comparison of two designs for the multifunction vehicle bus. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (5) (2006)
Armando Astarloa, Unai Bidarte, Jesús Lázaro, Aitzol Zuloaga, Jagoba Arias
Multiprocessor SoPC-Core for FAT volume computation. Microprocess. Microsystems 29 (10) (2005)
José L. Martín-Sánchez, Aitzol Zuloaga, Carlos Cuadrado, Jesús Lázaro, Unai Bidarte
Hardware implementation of optical flow constraint equation using FPGAs. Comput. Vis. Image Underst. 98 (3) (2005)
Armando Astarloa, Jesús Lázaro, Unai Bidarte, José Luis Martín, Aitzol Zuloaga
A Self-Reconfiguration Framework for Multiprocessor CSoPCs. FPL (2004)
Armando Astarloa, Jesús Lázaro, Jagoba Arias, Unai Bidarte, Aitzol Zuloaga
Co-simulation Virtual Platform for Reconfigurable Multiprocessor Hybrid Cores Development. MSV/AMCS (2004)
Unai Bidarte, Armando Astarloa, José Luis Martín, Jon Andreu
Simulation Platform for Architectural Verification and Performance Analysis in Core-Based SoC Design. FPL (2004)
Jesús Lázaro, Armando Astarloa, Jagoba Arias, Unai Bidarte, Carlos Cuadrado
High Throughput Serpent Encryption Implementation. FPL (2004)
Unai Bidarte, Armando Astarloa, Aitzol Zuloaga, Jaime Jimenez, Iñigo Martínez de Alegría
Core-Based Reusable Architecture for Slave Circuits with Extensive Data Exchange Requirements. FPL (2003)