Synchronization of faulty processors in coarse-grained TMR protected partially reconfigurable FPGA designs.
Uli KretzschmarJulen Gomez-CornejoArmando AstarloaUnai BidarteJavier Del SerPublished in: Reliab. Eng. Syst. Saf. (2016)
Keyphrases
- coarse grained
- field programmable gate array
- shared memory
- multithreading
- parallel computing
- fine grained
- power reduction
- hardware implementation
- systolic array
- parallel architecture
- digital signal
- general purpose processors
- parallel algorithm
- massively parallel
- processing elements
- reconfigurable hardware
- low cost
- parallel computation
- message passing
- distributed memory
- parallel computers
- hardware architecture
- image processing algorithms
- embedded systems
- protein sequences
- parallel processing
- signal processing
- computing systems
- high level
- power consumption
- access control
- contact maps
- feature selection
- energy landscape