Aitzol Zuloaga

Publication Activity (10 Years)

Years Active: 1998-2024
Publications (10 Years): 4

Top Topics

High Reliability

Top Venues

IEEE Trans. Reliab.

Microprocess. Microsystems

Publications

Jesús Lázaro, Armando Astarloa, Aitzol Zuloaga, José Ángel Araujo, Jaime Jiménez
AXI Lite Redundant On-Chip Bus Interconnect for High Reliability Systems. IEEE Trans. Reliab. 73 (1) (2024)
Julen Gomez-Cornejo, Igor Villalta, Itxaso Aranzabal, Iraide Lopez, Aitzol Zuloaga
Data content scrubbing approach for SRAM based FPGA designs. ISIE (2022)
Julen Gomez-Cornejo, Aitzol Zuloaga, Igor Villalta, Javier Del Ser, Uli Kretzschmar, Jesús Lázaro
A novel BRAM content accessing and processing method based on FPGA configuration bitstream. Microprocess. Microsystems 49 (2017)
Armando Astarloa, Unai Bidarte, Jaime Jimenez, Aitzol Zuloaga, Jesús Lázaro
Intelligent gateway for Industry 4.0-compliant production. IECON (2016)
José Araujo, Jesús Lázaro, Armando Astarloa, Aitzol Zuloaga, Jose Ignacio Garate
PRP and HSR for High Availability Networks in Power Utility Automation: A Method for Redundant Frames Discarding. IEEE Trans. Smart Grid 6 (5) (2015)
Aitzol Zuloaga, Armando Astarloa, Jaime Jimenez, Jesús Lázaro, Jose Angel Araujo
Cost-effective redundancy for ethernet train communications using HSR. ISIE (2014)
José Ángel Araujo, Jesús Lázaro, Armando Astarloa, Aitzol Zuloaga, Alain García
PRP and HSR version 1 (IEC 62439-3 Ed.2), improvements and a prototype implementation. IECON (2013)
José Ángel Araujo, Jesús Lázaro, Armando Astarloa, Aitzol Zuloaga, Naiara Moreira
Duplicate and circulating frames discard methods for PRP and HSR (IEC62439-3). IECON (2013)
Julen Gomez-Cornejo, Aitzol Zuloaga, Uli Kretzschmar, Unai Bidarte, Jaime Jimenez
Fast context reloading lockstep approach for SEUs mitigation in a FPGA soft core processor. IECON (2013)
Armando Astarloa, Jesús Lázaro, Unai Bidarte, Aitzol Zuloaga, Mikel Idirin
System-on-Chip implementation of Reliable Ethernet Networks nodes. IECON (2013)
Jose Angel Araujo, Jesús Lázaro, Armando Astarloa, Aitzol Zuloaga, Alain García
High availability automation networks: PRP and HSR ring implementations. ISIE (2012)
Jesús Lázaro, Armando Astarloa, Aitzol Zuloaga, Unai Bidarte, Jaime Jimenez
I2CSec: A secure serial Chip-to-Chip communication protocol. J. Syst. Archit. 57 (2) (2011)
Uli Kretzschmar, Armando Astarloa, Jesús Lázaro, Jaime Jimenez, Aitzol Zuloaga
An automatic experimental set-up for robustness analysis of designs implemented on SRAM FPGAS. SoC (2011)
Oscar Daniel Diaz, Armando Astarloa, Aitzol Zuloaga, Jesús Lázaro, Jaime Jimenez
NoCmodel: An extensible framework for Network-on-Chips modeling. ReCoSoC (2011)
Armando Astarloa, Jesús Lázaro, Unai Bidarte, Aitzol Zuloaga, José Luis Martín
An Autonomous Fault Tolerant System for CAN Communications. IEA/AIE (3) (2010)
Jesús Lázaro, Armando Astarloa, Unai Bidarte, Jaime Jimenez, Aitzol Zuloaga
AES-Galois Counter Mode Encryption/Decryption FPGA Core for Industrial and Residential Gigabit Ethernet Communications. ARC (2009)
Armando Astarloa, Jesús Lázaro, Unai Bidarte, Aitzol Zuloaga, Jaime Jimenez
PCIREX: A Fast Prototyping Platform for TMR Dynamically Reconfigurable Systems. ReConFig (2009)
Armando Astarloa, Jesús Lázaro, Unai Bidarte, Aitzol Zuloaga, Jaime Jimenez
DNAX-BCU: An Un-clonable Cost-conscious SoPC Implementation for Bus Coupling Units of the European Installation Bus. ICDCS Workshops (2009)
Itziar Marín, Aitzol Zuloaga, Iker Losada
A Novel Technique for Low Latency Data Gathering in Wireless Sensor Networks. DSD (2008)
Itziar Marín, Jagoba Arias, E. Arceredillo, Aitzol Zuloaga, Iker Losada, J. Mabe
LL-MAC: A low latency MAC protocol for wireless self-organised networks. Microprocess. Microsystems 32 (4) (2008)
Armando Astarloa, Aitzol Zuloaga, Unai Bidarte, José Luis Martín, Jesús Lázaro, Jaime Jimenez
Tornado: A self-reconfiguration control system for core-based multiprocessor CSoPCs. J. Syst. Archit. 53 (9) (2007)
Jesús Lázaro, Jagoba Arias, Armando Astarloa, Unai Bidarte, Aitzol Zuloaga
Hardware architecture for a general regression neural network coprocessor. Neurocomputing 71 (1-3) (2007)
Jaime Jimenez, José Luis Martín, Unai Bidarte, Armando Astarloa, Aitzol Zuloaga
Design of a Master Device for the Multifunction Vehicle Bus. IEEE Trans. Veh. Technol. 56 (6) (2007)
Jagoba Arias, Jesús Lázaro, Aitzol Zuloaga, Jaime Jimenez, Armando Astarloa
GPS-less location algorithm for wireless sensor networks. Comput. Commun. 30 (14-15) (2007)
Jesús Lázaro, Jagoba Arias, José Luis Martín, Aitzol Zuloaga, Carlos Cuadrado
SOM Segmentation of gray scale images for optical recognition. Pattern Recognit. Lett. 27 (16) (2006)
Jaime Jimenez, José Luis Martín, Aitzol Zuloaga, Unai Bidarte, Jagoba Arias
Comparison of two designs for the multifunction vehicle bus. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (5) (2006)
Jagoba Arias, Eduardo Santos, Itziar Marín, Jaime Jimenez, Jesús Lázaro, Aitzol Zuloaga
Node Synchronization in Wireless Sensor Networks. ICWMC (2006)
Armando Astarloa, Unai Bidarte, Jesús Lázaro, Aitzol Zuloaga, Jagoba Arias
Multiprocessor SoPC-Core for FAT volume computation. Microprocess. Microsystems 29 (10) (2005)
José L. Martín-Sánchez, Aitzol Zuloaga, Carlos Cuadrado, Jesús Lázaro, Unai Bidarte
Hardware implementation of optical flow constraint equation using FPGAs. Comput. Vis. Image Underst. 98 (3) (2005)
Armando Astarloa, Jesús Lázaro, Unai Bidarte, José Luis Martín, Aitzol Zuloaga
A Self-Reconfiguration Framework for Multiprocessor CSoPCs. FPL (2004)
Jagoba Arias, Jesús Lázaro, Aitzol Zuloaga, Jaime Jimenez
Doppler Location Algorithm for Wireless Sensor Networks. International Conference on Wireless Networks (2004)
Armando Astarloa, Jesús Lázaro, Jagoba Arias, Unai Bidarte, Aitzol Zuloaga
Co-simulation Virtual Platform for Reconfigurable Multiprocessor Hybrid Cores Development. MSV/AMCS (2004)
Jagoba Arias, Aitzol Zuloaga, Jesús Lázaro, Jon Andreu, Armando Astarloa
Malguki: an RSSI based ad hoc location algorithm. Microprocess. Microsystems 28 (8) (2004)
Unai Bidarte, Armando Astarloa, Aitzol Zuloaga, Jaime Jimenez, Iñigo Martínez de Alegría
Core-Based Reusable Architecture for Slave Circuits with Extensive Data Exchange Requirements. FPL (2003)
José Luis Martín, Aitzol Zuloaga, Josu Cruzado
Software Workbench for Movement Estimation based on Optical Flow Computation. VIIP (2001)
Aitzol Zuloaga, José Luis Martín, Joseba Ezquerra
Hardware Architecture for Optical Flow Estimation in Real Time. ICIP (3) (1998)