Suneui Park

Publication Activity (10 Years)

Years Active: 2017-2023
Publications (10 Years): 12

Top Topics

Arithmetic Operations

Power Consumption

Top Venues

IEEE J. Solid State Circuits

Publications

Yoonseo Cho, Jeonghyun Lee, Suneui Park, Seyeon Yoo, Jaehyouk Choi
A 122fsrms-Jitter and -60dBc-Reference-Spur 12.24GHz MDLL with a 102 - Multiplication Factor Using a Power-Gating Technique. VLSI Technology and Circuits (2023)
Suneui Park, Seyeon Yoo, Yuhwan Shin, Jeonghyun Lee, Jaehyouk Choi
A Sub-100 fs-Jitter 8.16-GHz Ring-Oscillator-Based Power-Gating Injection-Locked Clock Multiplier With the Multiplication Factor of 68. IEEE J. Solid State Circuits 58 (1) (2023)
Jooeun Bang, Jaeho Kim, Seohee Jung, Suneui Park, Jaehyouk Choi
A $47\text{fs}_{\text{rms}}$-Jitter and 26.6mW 103.5GHz PLL with Power-Gating Injection-Locked Frequency-Multiplier-Based Phase Detector and Extended Loop Bandwidth. ISSCC (2023)
Suneui Park, Seojin Choi, Seyeon Yoo, Yoonseo Cho, Jaehyouk Choi
An Ultra-Low Jitter, Low-Power, 102-GHz PLL Using a Power-Gating Injection-Locked Frequency Multiplier-Based Phase Detector. IEEE J. Solid State Circuits 57 (9) (2022)
Suneui Park, Seyeon Yoo, Yuhwan Shin, Jeonghyun Lee, Jaehyouk Choi
A 97fsrms-Jitter and 68-Multiplication Factor, 8.16GHz Ring-Oscillator Injection-Locked Clock Multiplier with Power-Gating Injection-Locking and Background Multi-Functional Digital Calibrator. ISSCC (2022)
Seyeon Yoo, Suneui Park, Seojin Choi, Yoonseo Cho, Heein Yoon, Chanwoong Hwang, Jaehyouk Choi
An 82fsrms-Jitter and 22.5mW-Power, 102GHz W-Band PLL Using a Power-Gating Injection-Locked Frequency-Multiplier- Based Phase Detector in 65nm CMOS. ISSCC (2021)
Heein Yoon, Suneui Park, Jaehyouk Choi
A Low-Jitter Injection-Locked Multi-Frequency Generator Using Digitally Controlled Oscillators and Time-Interleaved Calibration. IEEE J. Solid State Circuits 54 (6) (2019)
Heein Yoon, Juyeop Kim, Suneui Park, Younghyun Lim, Yongsun Lee, Jooeun Bang, Kyoohyun Lim, Jaehyouk Choi
A -31dBc integrated-phase-noise 29GHz fractional-N frequency synthesizer supporting multiple frequency bands for backward-compatible 5G using a frequency doubler and injection-locked frequency multipliers. ISSCC (2018)
Younghyun Lim, Jeonghyun Lee, Suneui Park, Jaehyouk Choi
An external-capacitor-less high-PSR low-dropout regulator using an adaptive supply-ripple cancellation technique to the body-gate. ASP-DAC (2018)
Younghyun Lim, Jeonghyun Lee, Suneui Park, Yongwoo Jo, Jaehyouk Choi
An External Capacitorless Low-Dropout Regulator With High PSR at All Frequencies From 10 kHz to 1 GHz Using an Adaptive Supply-Ripple Cancellation Technique. IEEE J. Solid State Circuits 53 (9) (2018)
Younghyun Lim, Jeonghyun Lee, Suneui Park, Jaehyouk Choi
An extemal-capacitor-less low-dropout regulator with less than -36dB PSRR at all frequencies from 10kHz to 1GHz using an adaptive supply-ripple cancellation technique to the body-gate. CICC (2017)
Suneui Park, Heein Yoon, Jaehyouk Choi
An ultra-low phase noise all-digital multi-frequency generator using injection-locked DCOs and time-interleaved calibration. A-SSCC (2017)