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Yoonseo Cho
ORCID
Publication Activity (10 Years)
Years Active: 2019-2023
Publications (10 Years): 6
Top Topics
Rms Error
Clock Frequency
Surgical Instruments
Power Consumption
Top Venues
ISSCC
IEEE J. Solid State Circuits
CICC
VLSI Technology and Circuits
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Publications
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Jeonghyun Lee
,
Yoonseo Cho
,
Jintae Kim
,
Jaehyouk Choi
A 0.009mm2, 6.5mW, 6.2b-ENOB 2.5GS/s Flash-and-VCO-Based Subranging ADC Using a Resistor-Ladder-Based Residue Shifter.
CICC
(2023)
Yoonseo Cho
,
Jeonghyun Lee
,
Suneui Park
,
Seyeon Yoo
,
Jaehyouk Choi
A 122fsrms-Jitter and -60dBc-Reference-Spur 12.24GHz MDLL with a 102 - Multiplication Factor Using a Power-Gating Technique.
VLSI Technology and Circuits
(2023)
Suneui Park
,
Seojin Choi
,
Seyeon Yoo
,
Yoonseo Cho
,
Jaehyouk Choi
An Ultra-Low Jitter, Low-Power, 102-GHz PLL Using a Power-Gating Injection-Locked Frequency Multiplier-Based Phase Detector.
IEEE J. Solid State Circuits
57 (9) (2022)
Seyeon Yoo
,
Suneui Park
,
Seojin Choi
,
Yoonseo Cho
,
Heein Yoon
,
Chanwoong Hwang
,
Jaehyouk Choi
An 82fsrms-Jitter and 22.5mW-Power, 102GHz W-Band PLL Using a Power-Gating Injection-Locked Frequency-Multiplier- Based Phase Detector in 65nm CMOS.
ISSCC
(2021)
Juyeop Kim
,
Heein Yoon
,
Younghyun Lim
,
Yongsun Lee
,
Yoonseo Cho
,
Taeho Seong
,
Jaehyouk Choi
A 76fsrms Jitter and -40dBc Integrated-Phase-Noise 28-to-31GHz Frequency Synthesizer Based on Digital Sub-Sampling PLL Using Optimally Spaced Voltage Comparators and Background Loop-Gain Optimization.
ISSCC
(2019)
Juyeop Kim
,
Younghyun Lim
,
Heein Yoon
,
Yongsun Lee
,
Hangi Park
,
Yoonseo Cho
,
Taeho Seong
,
Jaehyouk Choi
An Ultra-Low-Jitter, mmW-Band Frequency Synthesizer Based on Digital Subsampling PLL Using Optimally Spaced Voltage Comparators.
IEEE J. Solid State Circuits
54 (12) (2019)