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An 82fsrms-Jitter and 22.5mW-Power, 102GHz W-Band PLL Using a Power-Gating Injection-Locked Frequency-Multiplier- Based Phase Detector in 65nm CMOS.

Seyeon YooSuneui ParkSeojin ChoiYoonseo ChoHeein YoonChanwoong HwangJaehyouk Choi
Published in: ISSCC (2021)
Keyphrases
  • power consumption
  • clock gating
  • low power
  • power management
  • cmos technology
  • clock frequency
  • power reduction
  • power dissipation
  • phase difference
  • low cost