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A 122fsrms-Jitter and -60dBc-Reference-Spur 12.24GHz MDLL with a 102 - Multiplication Factor Using a Power-Gating Technique.
Yoonseo Cho
Jeonghyun Lee
Suneui Park
Seyeon Yoo
Jaehyouk Choi
Published in:
VLSI Technology and Circuits (2023)
Keyphrases
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real time
power consumption
high speed
floating point
arithmetic operations
packet loss
factor analysis
database
multiresolution
low power
computational power
end to end delay
power distribution