Steven G. Rothweiler

Publication Activity (10 Years)

Years Active: 1988-1997
Publications (10 Years): 0

Publications

Srimat T. Chakradhar, Vijay Gangaram, Steven G. Rothweiler
Deriving Signal Constraints to Accelerate Sequential Test Generation. VLSI Design (1997)
Srimat T. Chakradhar, Steven G. Rothweiler, Vishwani D. Agrawal
Redundancy removal and test generation for circuits with non-Boolean primitives. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16 (11) (1997)
Srimat T. Chakradhar, Steven G. Rothweiler
Redundancy Removal and Test Generation for Circuits with Non-Boolean Primitives. VTS (1995)
Srimat T. Chakradhar, Vishwani D. Agrawal, Steven G. Rothweiler
A transitive closure algorithm for test generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12 (7) (1993)
Srimat T. Chakradhar, Sujit Dey, Miodrag Potkonjak, Steven G. Rothweiler
Sequential Circuit Delay optimization Using Global Path Delays. DAC (1993)
Sujit Dey, Miodrag Potkonjak, Steven G. Rothweiler
Performance optimization of sequential circuits by eliminating retiming bottlenecks. ICCAD (1992)
Chia-Jeng Tseng, Steven G. Rothweiler, Shailesh Sutarwala, Ajit M. Prabhu
Mind: a module binder for high level synthesis. ICCD (1989)
Ruey-Sing Wei, Steven G. Rothweiler, Jing-Yang Jou
BECOME: Behavior Level Circuit Synthesis Based on Structure Mapping. DAC (1988)
Chia-Jeng Tseng, Ruey-Sing Wei, Steven G. Rothweiler, Michael M. Tong, Ajoy K. Bose
Bridge: A Versatile Behavioral Synthesis System. DAC (1988)