Renato Stefanelli

Publication Activity (10 Years)

Years Active: 1971-2011
Publications (10 Years): 0

Publications

Marco D. Santambrogio, Renato Stefanelli
A New Compact SD2 Positive Integer Triangular Array Division Circuit. IEEE Trans. Very Large Scale Integr. Syst. 19 (1) (2011)
Fabio Salice, Mariagiovanna Sami, Renato Stefanelli
Fault-Tolerant CAM Architectures: A Design Framework. DFT (2002)
Donatella Sciuto, Cristina Silvano, Renato Stefanelli
Systematic AUED Codes for Self-Checking Architectures. DFT (1998)
Fausto Distante, Mariagiovanna Sami, Renato Stefanelli
Harvesting Through Array Partitioning: A Solution to Achieve Defect Tolerance. DFT (1997)
Fausto Distante, Mariagiovanna Sami, Renato Stefanelli
Array partitioning to achieve defect tolerance. EUROMICRO (1997)
Cristiana Bolchini, Giacomo Buonanno, M. Cozzini, Donatella Sciuto, Renato Stefanelli
Designing Ad-Hoc Codes for the Realization of Fault Tolerant CMOS Networks. DFT (1997)
Cristiana Bolchini, Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli
Fault detection and fault tolerance issues at CMOS level through AUED encoding. DFT (1996)
Giovanni A. Mojoli, Davide Salvi, M. G. Sami, Giacomo R. Sechi, Renato Stefanelli
KITE: a behavioural approach to fault-tolerance in FPGA-based systems. DFT (1996)
Mariagiovanna Sami, Fausto Distante, Renato Stefanelli
A Channel-Constrained Reconfiguration Approach for Processing Arrays. DFT (1995)
Cristiana Bolchini, Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli
A new switching-level approach to multiple-output functions synthesis. VLSI Design (1995)
Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli
Innovative Structures for CMOS Combinational Gates Synthesis. IEEE Trans. Computers 43 (4) (1994)
Cristiana Bolchini, Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli
A CMOS Fault Tolerant Architecture for Swith-Level Faults. DFT (1994)
Cristiana Bolchini, Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli
CMOS Reliability Improvements Through a New Fault Tolerant Technique. ISCAS (1994)
Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli
New CMOS Structures for the Synthesis of Dominant Functions. VLSI Design (1993)
M. G. Sami, Donatella Sciuto, Renato Stefanelli
Concurrently self-checking structures for Fsms. Microprocess. Microprogramming 39 (2-5) (1993)
A. Dell'Acqua, M. Hansen, Sami J. Inkinen, B. Lofstedt, J. P. Vanuxem, Christer Svensson, Jiren Yuan, H. Hentzell, L. Del Buono, J. David, J. F. Genat, H. Lebbolo, O. LeDortz, P. Nayman, Aurore Savoy-Navarro, R. Zitoun, Cesare Alippi, Luca Breveglieri, Luigi Dadda, Vincenzo Piuri, Fabio Salice, Mariagiovanna Sami, Renato Stefanelli, P. Cattaneo, G. Fumagalli, G. Goggi, Simona Brigati, Umberto Gatti, Franco Maloberti, Guido Torelli, P. Carlson, A. Kerek, Goran Appelquist, S. Berglund, C. Bohm, Magnus Engström, N. Yamdagni, Rolf Sundblad, I. Höglund, S. T. Persson
System Level Policies for Fault Tolerance Issues in the FERMI Project. DFT (1993)
Luigi Dadda, Vincenzo Piuri, Renato Stefanelli
Multi-parallel convolvers. IEEE Symposium on Computer Arithmetic (1993)
Vincenzo Piuri, Mariagiovanna Sami, Donatella Sciuto, Renato Stefanelli
A behavioral approach to testability analysis for neural networks. Microprocess. Microprogramming 35 (1-5) (1992)
Vincenzo Piuri, Renato Stefanelli
Fault-tolerant techniques for VLSI tree structures. Microprocess. Microprogramming 34 (1-5) (1992)
Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli
Optimization techniques for multiple output function synthesis. EURO-DAC (1991)
Fausto Distante, Mariagiovanna Sami, Renato Stefanelli, Giancarlo Storti-Gajan
Mapping neural nets onto a massively parallel architecture: a defect-tolerance solution. Proc. IEEE 79 (4) (1991)
Vincenzo Piuri, Renato Stefanelli
Concurrent error detection in parallel multipliers and complex arithmetic structures: Remarks on the use of the 3n code. Microprocessing and Microprogramming 31 (1-5) (1991)
Virginio Cantoni, V. Gesu, Marco Ferretti, Stefano Levialdi, Roberto M. Negrini, Renato Stefanelli
The PAPIA system. J. VLSI Signal Process. 2 (4) (1991)
Fausto Distante, M. G. Sami, Renato Stefanelli, Giancarlo Storti Gajani
Area compaction in silicon structures for neural net implementation. Microprocessing and Microprogramming 28 (1-5) (1990)
Fabrizio Lombardi, Mariagiovanna Sami, Renato Stefanelli
Reconfiguration of VLSI arrays by covering. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8 (9) (1989)
Fabrizio Lombardi, Donatella Sciuto, Renato Stefanelli
An algorithm for functional reconfiguration of fixed-size arrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7 (10) (1988)
Vincenzo Piuri, Renato Stefanelli, Giovanni Traverso
Error detection in serial multipliers and in systolic arrays: An approach based upon A★N codes. Microprocess. Microprogramming 23 (1-5) (1988)
Vincenzo Piuri, Renato Stefanelli
Use of redundant binary representation for fault-tolerant arithmetic array processors. ICCD (1988)
Fabrizio Lombardi, Donatella Sciuto, Renato Stefanelli
A Technique for Reconfiguring Two Dimensional VLSI Arrays. RTSS (1987)
Roberto M. Negrini, Mariagiovanna Sami, Renato Stefanelli
Fault Tolerance Fechniques for Array Structures Used in Supercomputing. Computer 19 (2) (1986)
Mariagiovanna Sami, Renato Stefanelli
Reconfigurable architectures for VLSI processing arrays. Proc. IEEE 74 (5) (1986)
Renato Stefanelli
A comment on an investigation into the skeletonization approach of Hilditch. Pattern Recognit. 19 (1) (1986)
Virginio Cantoni, Marco Ferretti, Stefano Levialdi, Renato Stefanelli
PAPIA: Pyramidal architecture for parallel image analysis. IEEE Symposium on Computer Arithmetic (1985)
Marco Annaratone, Renato Stefanelli
A multiplier with multiple error correction capability. IEEE Symposium on Computer Arithmetic (1983)
Mariagiovanna Sami, Renato Stefanelli
Reconfigurable architectures for VLSI processing arrays. AFIPS National Computer Conference (1983)
Mariagiovanna Sami, Renato Stefanelli
Compression algorithms that preserve basic topological features in binary-coded patterns. Pattern Recognit. 5 (2) (1973)
Renato Stefanelli
A Suggestion for a High-Speed Parallel Binary Divider. IEEE Trans. Computers 21 (1) (1972)
Renato Stefanelli, Azriel Rosenfeld
Some Parallel Thinning Algorithms for Digital Pictures. J. ACM 18 (2) (1971)