Jiren Yuan

Publication Activity (10 Years)

Years Active: 1993-2007
Publications (10 Years): 0

Publications

Cheng Chen, Jiren Yuan
A 10-bit 500-MS/s 124-mW Subranging Folding ADC in 0.13 µm CMOS. ISCAS (2007)
Johan Piper, Jiren Yuan
Design considerations of a floating-point ADC with embedded S/H. ISCAS (6) (2005)
Gang Xu, Jiren Yuan
Performance analysis of general charge sampling. IEEE Trans. Circuits Syst. II Express Briefs (2) (2005)
Gang Xu, Jiren Yuan
A CMOS 500 MS/S charge sampler. Circuits, Signals, and Systems (2004)
Gang Xu, Jiren Yuan
A programmable analog-to-digital converter. ISCAS (1) (2004)
Gang Xu, Jiren Yuan
Performance analysis of general charge sampling. ISCAS (1) (2003)
Gang Xu, Jiren Yuan
A Differential Difference Comparator for multi-step A/D converters. ISCAS (1) (2003)
Yijun Zhou, Jiren Yuan
A highly integrated CMOS direct digital RF quadrature modulator. ESSCIRC (2003)
Lixin Yang, Jiren Yuan
An arbitrarily skewable multiphase clock generator combining direct interpolation with phase error average. ISCAS (1) (2003)
Yijun Zhou, Jiren Yuan
A 10-bit wide-band CMOS direct digital RF amplitude modulator. IEEE J. Solid State Circuits 38 (7) (2003)
Yijun Zhou, Jiren Yuan
An 8-bit 100-MHz CMOS linear interpolation DAC. IEEE J. Solid State Circuits 38 (10) (2003)
Yijun Zhou, Jiren Yuan
A direct digital RF amplitude modulator. ISCAS (1) (2002)
Lixin Yang, Yijun Zhou, Jiren Yuan
A non-feedback multiphase clock generator. ISCAS (4) (2002)
Gang Xu, Jiren Yuan
An embedded low power FIR filter. ISCAS (4) (2001)
Johan Piper, Jiren Yuan
Realization of a floating-point A/D converter. ISCAS (1) (2001)
Yijun Zhou, Jiren Yuan
An 8-Bit, 100-MHz low glitch interpolation DAC. ISCAS (4) (2001)
Roland Strandberg, Jiren Yuan
Single input current-sensing differential logic (SCSDL). ISCAS (2000)
Jiren Yuan, Johan Piper
Floating-point analog-to-digital converter. ICECS (1999)
Jiren Yuan, Christer Svensson
New single-clock CMOS latches and flipflops with improved speed and power savings. IEEE J. Solid State Circuits 32 (1) (1997)
Crister Svensson, Jiren Yuan
A 3-level asynchronous protocol for a differential two-wire communication link. IEEE J. Solid State Circuits 29 (9) (1994)
Jiren Yuan, Crister Svensson
A 10-bit 5-MS/s successive approximation ADC cell used in a 70-MS/s ADC array in 1.2-μm CMOS. IEEE J. Solid State Circuits 29 (8) (1994)
Christer Svensson, Jiren Yuan
Ultra high speed CMOS design. VLSI (1993)
A. Dell'Acqua, M. Hansen, Sami J. Inkinen, B. Lofstedt, J. P. Vanuxem, Christer Svensson, Jiren Yuan, H. Hentzell, L. Del Buono, J. David, J. F. Genat, H. Lebbolo, O. LeDortz, P. Nayman, Aurore Savoy-Navarro, R. Zitoun, Cesare Alippi, Luca Breveglieri, Luigi Dadda, Vincenzo Piuri, Fabio Salice, Mariagiovanna Sami, Renato Stefanelli, P. Cattaneo, G. Fumagalli, G. Goggi, Simona Brigati, Umberto Gatti, Franco Maloberti, Guido Torelli, P. Carlson, A. Kerek, Goran Appelquist, S. Berglund, C. Bohm, Magnus Engström, N. Yamdagni, Rolf Sundblad, I. Höglund, S. T. Persson
System Level Policies for Fault Tolerance Issues in the FERMI Project. DFT (1993)