Neeta Pandey

Publication Activity (10 Years)

Years Active: 2005-2024
Publications (10 Years): 49

Top Topics

Comparative Analysis

Positive And Negative

Top Venues

Microelectron. J.

J. Circuits Syst. Comput.

Int. J. Circuit Theory Appl.

Publications

Lokesh Soni, Neeta Pandey
A low power Schmitt-trigger driven 10T SRAM Cell for high speed applications. Integr. 97 (2024)
Neetika Yadav, Neeta Pandey, Deva Nand
Modified Dual Mode Transmission Gate Diffusion Input Logic for Improving Energy Efficiency. J. Circuits Syst. Comput. 32 (10) (2023)
Navnit Kumar, Manjeet Kumar, Neeta Pandey
Electronically tunable positive and negative fractional order inductor circuit using single topology. Integr. 88 (2023)
Kriti Suneja, Neeta Pandey, Rajeshwari Pandey
A Novel Chaotic System with Exponential Nonlinearity and its Adaptive Self-Synchronization: From Numerical Simulations to Circuit Implementation. J. Circuits Syst. Comput. 32 (17) (2023)
Sumedha Gupta, Neeta Pandey, R. S. Gupta
Modeling of Dual- Metal Junctionless Accumulation-Mode cylindrical surrounding gate (DM-JAM-CSG) MOSFET for cryogenic temperature applications. Microelectron. J. 139 (2023)
Ishu Tomar, Indu Sreedevi, Neeta Pandey
PLC and SCADA based Real Time Monitoring and Train Control System for the Metro Railways Infrastructure. Wirel. Pers. Commun. 129 (1) (2023)
Shikha, Neeta Pandey, Kirti Gupta
Memristor-Based Architectures for PFSCL Circuit Realizations. Circuits Syst. Signal Process. 42 (8) (2023)
Neetika Yadav, Neeta Pandey, Deva Nand
LDML: A Proposal to Reduce Leakage Power in DML Circuits. Wirel. Pers. Commun. 129 (2) (2023)
Damyanti Singh, Neeta Pandey, Kirti Gupta
Process invariant Schmitt Trigger non-volatile 13T1M SRAM cell. Microelectron. J. 135 (2023)
Om Krishna Gupta, Neeta Pandey, Maneesha Gupta
Refining RNMC compensation for Three Stage Amplifier using DTMOS Transistor and FFVF. ICCCNT (2023)
Navnit Kumar, Manjeet Kumar, Neeta Pandey
CCTA based four different pairs of mutually coupled circuit using single topology. Integr. 91 (2023)
Monika Bhardwaj, Sujata Pandey, Neeta Pandey
A novel design of a 1 GHz phase locked loop with improved lock time for fast frequency acquisition. Int. J. Comput. Aided Eng. Technol. 17 (2) (2022)
Ranjana Sivaram, Kirti Gupta, Neeta Pandey
On improving the performance of dynamic positive-feedback source-coupled logic (D-PFSCL) through inclusion of transmission gates. Microprocess. Microsystems 90 (2022)
Kriti Suneja, Neeta Pandey, Rajeshwari Pandey
Novel Pehlivan-Uyarŏglu Chaotic System Variants and their CFOA Based Realization. J. Circuits Syst. Comput. 31 (9) (2022)
Damyanti Singh, Kirti Gupta, Neeta Pandey
A novel read decoupled 8T1M nvSRAM cell for near threshold operation. Microelectron. J. 126 (2022)
Garima Varshney, Neeta Pandey, Rajeshwari Pandey
OTA Based Fractional-Order Oscillator With Controlled Phase Difference. ISCAS (2022)
Monica Gupta, Kirti Gupta, Neeta Pandey
A novel PVT-variation-tolerant Schmitt-trigger-based 12T SRAM cell with improved write ability and high ION/IOFF ratio in sub-threshold region. Int. J. Circuit Theory Appl. 49 (11) (2021)
Neetika Yadav, Neeta Pandey, Deva Nand
Leakage reduction in dual mode logic through gated leakage transistors. Microprocess. Microsystems 84 (2021)
R. Arundeepakvel, Jatin, Parth Khatter, Neeta Pandey, Shahram Minaei
A novel design for voltage inverting metamutator and its applications. Microelectron. J. 113 (2021)
Aditya S. Kumar, Sagar Jain, Neeta Pandey
Clock Aligned Input Adiabatic Logic. Microelectron. J. 114 (2021)
Monica Gupta, Kirti Gupta, Neeta Pandey
Comparative Analysis of the Design Techniques for Low Leakage SRAMs at 32nm. Microprocess. Microsystems 85 (2021)
Garima Varshney, Neeta Pandey, Rajeshwari Pandey
Generalization of shadow filters in fractional domain. Int. J. Circuit Theory Appl. 49 (10) (2021)
Monica Gupta, Kirti Gupta, Neeta Pandey
A data-independent 9T SRAM cell with enhanced ION/IOFF ratio and RBL voltage swing in near threshold and sub-threshold region. Int. J. Circuit Theory Appl. 49 (4) (2021)
Navnit Kumar, Manjeet Kumar, Neeta Pandey
Unified floating immittance emulator based on CCTA. Microelectron. J. 118 (2021)
Ranjana Sivaram, Kirti Gupta, Neeta Pandey
A new realization scheme for dynamic PFSCL style. Integr. 75 (2020)
Prakhar Sharma, Shourya Gupta, Kirti Gupta, Neeta Pandey
A low power subthreshold Schmitt Trigger based 12T SRAM bit cell with process-variation-tolerant write-ability. Microelectron. J. 97 (2020)
Gurumurthy Komanapalli, Rajeshwari Pandey, Neeta Pandey
Operational Transresistance Amplifier Based Wienbridge Oscillator and Its Harmonic Analysis. Wirel. Pers. Commun. 108 (1) (2019)
Praveen Kumar, Neeta Pandey, Sajal K. Paul
Realization of Resistorless and Electronically Tunable Inverse Filters Using VDTA. J. Circuits Syst. Comput. 28 (9) (2019)
Gurumurthy Komanapalli, Rajeshwari Pandey, Neeta Pandey
New sinusoidal oscillator configurations using operational transresistance amplifier. Int. J. Circuit Theory Appl. 47 (5) (2019)
Pranav Gangwar, Neeta Pandey, Rajeshwari Pandey
Novel Control Unit Design for a High-Speed SHA-3 Architecture. MWSCAS (2019)
Shourya Gupta, Kirti Gupta, Benton H. Calhoun, Neeta Pandey
Low-Power Near-Threshold 10T SRAM Bit Cells With Enhanced Data-Independent Read Port Leakage for Array Augmentation in 32-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2019)
Manoj Kumar Tiwari, Neeta Pandey, Sajal K. Paul, Saiyid Mohammad Irshad Rizvi
Programmable CCCII: reliability analysis and design methodology. IET Circuits Devices Syst. 13 (4) (2019)
Pranav Gangwar, Satvik Maurya, Shubham Garg, Sakshi Goyal, Aditya S. Kumar, Preyesh Dalmia, Neeta Pandey
Hardware/Software Co-Design of a High-Speed Othello Solver. MWSCAS (2019)
Rajeshwari Pandey, Neeta Pandey
OTRA Based Log and Antilog Amplifiers. MWSCAS (2018)
Shourya Gupta, Kirti Gupta, Neeta Pandey
Analysis of a Subthreshold 10T SRAM Bit Cell With Variation Tolerant Write and Divided Bit-Line Read. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2018)
Veepsa Bhatia, Neeta Pandey, Sri Ranjani Prasanthi
Design of an SCL logic based Current Comparator. MWSCAS (2018)
Neeta Pandey, Kirti Gupta, Bharat Choudhary
MCML Dynamic Register Design. MWSCAS (2018)
Preyesh Dalmia, Vikas, Abhinav Parashar, Akshi Tomar, Neeta Pandey
Novel High Speed Vedic Multiplier Proposal Incorporating Adder Based on Quaternary Signed Digit Number System. VLSI Design (2018)
Veepsa Bhatia, Neeta Pandey
Modified Tang and Pun's Current Comparator and Its Application to Full Flash and Two-Step Flash Current Mode ADCs. J. Electr. Comput. Eng. 2017 (2017)
Shourya Gupta, Kirti Gupta, Neeta Pandey
A 32-nm Subthreshold 7T SRAM Bit Cell With Read Assist. IEEE Trans. Very Large Scale Integr. Syst. 25 (12) (2017)
Pratibha Bajpai, Neeta Pandey, Kirti Gupta, Shrey Bagga, Jeebananda Panda
On Improving the Performance of Dynamic DCVSL Circuits. J. Electr. Comput. Eng. 2017 (2017)
Neeta Pandey, Bharat Choudhary, Kirti Gupta, Ankit Mittal
New Sleep-Based PFSCL Tri-State Inverter/Buffer Topologies. J. Circuits Syst. Comput. 26 (12) (2017)
Naman Saxena, Shruti Dutta, Neeta Pandey, Kirti Gupta
Implementation and Performance Comparison of a Four-Bit Ripple-Carry Adder Using Different MOS Current Mode Logic Topologies. ICCSA (6) (2017)
Divyesh Sachan, Deva Nand, Neeta Pandey
Universal biquadratic filter using Operational Floating Current Conveyor (OFCC). ICM (2016)
Shobhit Kareer, Anchit Kumar, Kirti Gupta, Neeta Pandey
A Novel Bulk Drain Connected 6T SRAM Cell. ICACDS (2016)
Neeta Pandey, Deva Nand, Rajeshwari Pandey
Generalised operational floating current conveyor based instrumentation amplifier. IET Circuits Devices Syst. 10 (3) (2016)
Veepsa Bhatia, Neeta Pandey
A Novel Ultra Low Power Current Comparator. ICACDS (2016)
Neeta Pandey, Kirti Gupta, Bharat Choudhary
New Proposal for MCML Based Three-Input Logic Implementation. VLSI Design 2016 (2016)
Neeta Pandey, Kirti Gupta, Garima Bhatia, Bharat Choudhary
MOS current mode logic exclusive-OR gate using multi-threshold triple-tail cells. Microelectron. J. 57 (2016)
Neeta Pandey, Rajeshwari Pandey
Approach for third order quadrature oscillator realisation. IET Circuits Devices Syst. 9 (3) (2015)
Neeta Pandey, Kirti Gupta, Maneesha Gupta
An efficient triple-tail cell based PFSCL D latch. Microelectron. J. 45 (8) (2014)
Rajeshwari Pandey, Neeta Pandey, Sajal K. Paul, Ajay Singh, B. Sriram, Kaushlendra Trivedi
Novel grounded inductance simulator using single OTRA. Int. J. Circuit Theory Appl. 42 (10) (2014)
Kirti Gupta, Neeta Pandey, Maneesha Gupta
Analysis and design of MOS current mode logic exclusive-OR gate using triple-tail cells. Microelectron. J. 44 (6) (2013)
Neeta Pandey, Sajal K. Paul
Mixed Mode Universal filter. J. Circuits Syst. Comput. 22 (1) (2013)
Veepsa Bhatia, Neeta Pandey, Asok Bhattacharyya
An expandable current-mode ADC with power optimization technique. RAIT (2012)
Rajeshwari Pandey, Neeta Pandey, Sajal K. Paul, Aditya Singh, B. Sriram, Kaushalendra Trivedi
New Topologies of Lossless Grounded Inductor Using OTRA. J. Electr. Comput. Eng. 2011 (2011)
Neeta Pandey, Sajal K. Paul
Single CDTA-Based Current Mode All-Pass Filter and Its Applications. J. Electr. Comput. Eng. 2011 (2011)
Neeta Pandey, Sajal K. Paul
Differential Difference Current Conveyor Transconductance Amplifier: A New Analog Building Block for Signal Processing. J. Electr. Comput. Eng. 2011 (2011)
Neeta Pandey, Rishik Bazaz, Rahul Manocha
MO-CCCCTA-Based Floating Positive and Negative Inductors and Their Applications. J. Electr. Comput. Eng. 2011 (2011)
Kirti Gupta, Ranjana Sridhar, Jaya Chaudhary, Neeta Pandey, Maneesha Gupta
New Low-Power Tristate Circuits in Positive Feedback Source-Coupled Logic. J. Electr. Comput. Eng. 2011 (2011)
Rajeshwari Pandey, Neeta Pandey, Mayank Bothra, Sajal K. Paul
Operational Transresistance Amplifier-Based Multiphase Sinusoidal Oscillators. J. Electr. Comput. Eng. 2011 (2011)
Neeta Pandey, Sajal K. Paul
SIMO Transadmittance Mode Active-C Universal Filter. Circuits Syst. 1 (2) (2010)
Neeta Pandey, Sajal K. Paul, Asok Bhattacharyya, S. B. Jain
A new mixed mode biquad using reduced number of active and passive elements. IEICE Electron. Express 3 (6) (2006)
Neeta Pandey, Sajal K. Paul, Asok Bhattacharyya, S. B. Jain
A novel current controlled current mode universal filter: SITO approach. IEICE Electron. Express 2 (17) (2005)
Neeta Pandey, Sajal K. Paul, Asok Bhattacharyya
An insensitive current mode universal biquad: multi-input multi-output. ISCAS (4) (2005)