Login / Signup
Low-Power Near-Threshold 10T SRAM Bit Cells With Enhanced Data-Independent Read Port Leakage for Array Augmentation in 32-nm CMOS.
Shourya Gupta
Kirti Gupta
Benton H. Calhoun
Neeta Pandey
Published in:
IEEE Trans. Circuits Syst. I Regul. Pap. (2019)
Keyphrases
</>
low power
power consumption
high speed
low cost
cmos technology
high power
data integrity
image sensor
single chip
wireless networks
vlsi circuits