Kirti Gupta

Publication Activity (10 Years)

Years Active: 2011-2024
Publications (10 Years): 30

Top Topics

Iris Recognition

Recurrent Neural Networks

Top Venues

Microelectron. J.

IEEE Trans. Circuits Syst. I Regul. Pap.

IEEE Trans. Smart Grid

Publications

Kirti Gupta, Bijaya Ketan Panigrahi, Anupam Joshi, Kolin Paul
Demonstration of denial of charging attack on electric vehicle charging infrastructure and its consequences. Int. J. Crit. Infrastructure Prot. 46 (2024)
Kirti Gupta, Subham Sahoo, Bijaya Ketan Panigrahi
A Monolithic Cybersecurity Architecture for Power Electronic Systems. CoRR (2024)
Kirti Gupta, Subham Sahoo, Bijaya Ketan Panigrahi
Delay-Aware Semantic Sampling in Power Electronic Systems. IEEE Trans. Smart Grid 15 (4) (2024)
Kirti Gupta, Subham Sahoo, Bijaya Ketan Panigrahi
Delay-Aware Semantic Sampling in Power Electronic Systems. CoRR (2024)
Kirti Gupta, Subham Sahoo, Bijaya Ketan Panigrahi
A Monolithic Cybersecurity Architecture for Power Electronic Systems. IEEE Trans. Smart Grid 15 (4) (2024)
Aditi Chauhan, Yashika Kukkar, Preeti Nagrath, Kirti Gupta, D. Jude Hemanth
Integrating LSTM and NLP techniques for essay generation. Intell. Decis. Technol. 18 (1) (2024)
Shikha, Neeta Pandey, Kirti Gupta
Memristor-Based Architectures for PFSCL Circuit Realizations. Circuits Syst. Signal Process. 42 (8) (2023)
Damyanti Singh, Neeta Pandey, Kirti Gupta
Process invariant Schmitt Trigger non-volatile 13T1M SRAM cell. Microelectron. J. 135 (2023)
Kirti Gupta, Subham Sahoo, Bijaya Ketan Panigrahi, Charalambos Konstantinou
Impact Assessment of Data Integrity Attacks in MVDC Shipboard Power Systems. CoRR (2023)
Aniket Kumar, Mehul Madaan, Shubham Kumar, Aniket Saha, Kirti Gupta
Handwriting Generation and Synthesis using Recurrent Neural Networks. ICCCNT (2022)
Ranjana Sivaram, Kirti Gupta, Neeta Pandey
On improving the performance of dynamic positive-feedback source-coupled logic (D-PFSCL) through inclusion of transmission gates. Microprocess. Microsystems 90 (2022)
Kirti Gupta, Parul Goyal
Test Suites Generation using UML Modelling and Heuristic Techniques: A Systematic Study. ICIMMI (2022)
Damyanti Singh, Kirti Gupta, Neeta Pandey
A novel read decoupled 8T1M nvSRAM cell for near threshold operation. Microelectron. J. 126 (2022)
Monica Gupta, Kirti Gupta, Neeta Pandey
A novel PVT-variation-tolerant Schmitt-trigger-based 12T SRAM cell with improved write ability and high ION/IOFF ratio in sub-threshold region. Int. J. Circuit Theory Appl. 49 (11) (2021)
Monica Gupta, Kirti Gupta, Neeta Pandey
Comparative Analysis of the Design Techniques for Low Leakage SRAMs at 32nm. Microprocess. Microsystems 85 (2021)
Georgios Effraimidis, Kirti Gupta, Urka Petrovcic
Was the Update of the 2015 Business Review Letter to the IEEE Justified? IEEE Commun. Stand. Mag. 5 (4) (2021)
Monica Gupta, Kirti Gupta, Neeta Pandey
A data-independent 9T SRAM cell with enhanced ION/IOFF ratio and RBL voltage swing in near threshold and sub-threshold region. Int. J. Circuit Theory Appl. 49 (4) (2021)
Ranjana Sivaram, Kirti Gupta, Neeta Pandey
A new realization scheme for dynamic PFSCL style. Integr. 75 (2020)
Prakhar Sharma, Shourya Gupta, Kirti Gupta, Neeta Pandey
A low power subthreshold Schmitt Trigger based 12T SRAM bit cell with process-variation-tolerant write-ability. Microelectron. J. 97 (2020)
Shourya Gupta, Kirti Gupta, Benton H. Calhoun, Neeta Pandey
Low-Power Near-Threshold 10T SRAM Bit Cells With Enhanced Data-Independent Read Port Leakage for Array Augmentation in 32-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2019)
Shourya Gupta, Kirti Gupta, Neeta Pandey
Analysis of a Subthreshold 10T SRAM Bit Cell With Variation Tolerant Write and Divided Bit-Line Read. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2018)
Neeta Pandey, Kirti Gupta, Bharat Choudhary
MCML Dynamic Register Design. MWSCAS (2018)
Shourya Gupta, Kirti Gupta, Neeta Pandey
A 32-nm Subthreshold 7T SRAM Bit Cell With Read Assist. IEEE Trans. Very Large Scale Integr. Syst. 25 (12) (2017)
Pratibha Bajpai, Neeta Pandey, Kirti Gupta, Shrey Bagga, Jeebananda Panda
On Improving the Performance of Dynamic DCVSL Circuits. J. Electr. Comput. Eng. 2017 (2017)
Neeta Pandey, Bharat Choudhary, Kirti Gupta, Ankit Mittal
New Sleep-Based PFSCL Tri-State Inverter/Buffer Topologies. J. Circuits Syst. Comput. 26 (12) (2017)
Naman Saxena, Shruti Dutta, Neeta Pandey, Kirti Gupta
Implementation and Performance Comparison of a Four-Bit Ripple-Carry Adder Using Different MOS Current Mode Logic Topologies. ICCSA (6) (2017)
Shobhit Kareer, Anchit Kumar, Kirti Gupta, Neeta Pandey
A Novel Bulk Drain Connected 6T SRAM Cell. ICACDS (2016)
Neeta Pandey, Kirti Gupta, Bharat Choudhary
New Proposal for MCML Based Three-Input Logic Implementation. VLSI Design 2016 (2016)
Neeta Pandey, Kirti Gupta, Garima Bhatia, Bharat Choudhary
MOS current mode logic exclusive-OR gate using multi-threshold triple-tail cells. Microelectron. J. 57 (2016)
Kirti Gupta, Rashmi Gupta
Multi-resolution wavelet-based image fusion for iris recognition. Int. J. Appl. Pattern Recognit. 2 (2) (2015)
Neeta Pandey, Kirti Gupta, Maneesha Gupta
An efficient triple-tail cell based PFSCL D latch. Microelectron. J. 45 (8) (2014)
Kirti Gupta, Neeta Pandey, Maneesha Gupta
Analysis and design of MOS current mode logic exclusive-OR gate using triple-tail cells. Microelectron. J. 44 (6) (2013)
Kirti Gupta, Ranjana Sridhar, Jaya Chaudhary, Neeta Pandey, Maneesha Gupta
New Low-Power Tristate Circuits in Positive Feedback Source-Coupled Logic. J. Electr. Comput. Eng. 2011 (2011)