LDML: A Proposal to Reduce Leakage Power in DML Circuits.

Neetika Yadav Neeta Pandey Deva Nand

Published in: Wirel. Pers. Commun. (2023)

Keyphrases

power consumption
chip design
image processing
power reduction
high speed
digital circuits
information retrieval
knowledge base
expert systems
email
low cost
machine learning
computational power
circuit design
analog circuits
asynchronous circuits
analog vlsi
real time