Michael Payer

Publication Activity (10 Years)

Years Active: 1980-2003
Publications (10 Years): 0

University of Hamburg, Germany (PHD)

Education History

University of Hamburg, Germany

PHD

Publications

Michael Payer
A Platform for Construction and Integration of Digital IP Blocks. MBMV (2003)
Michael Payer
Industrial Experience with Formal Verification (Industrielle Erfahrungen mit Formaler Verifikation). Informationstechnik Tech. Inform. 43 (1) (2001)
Michael Payer
Industrial Experience with Formal Verification. MBMV (2000)
Jörg Bormann, Jörg Lohse, Michael Payer, Gerd Venzl
Model Checking in Industrial Hardware Design. DAC (1995)
Jörg Biesenack, Michael Koster, Anton Langmaier, Stephane Ledeux, Sabine März, Michael Payer, Michael Pilsl, Steffen Rumler, Holger Soukup, Norbert Wehn, Peter Duzy
The Siemens high-level synthesis system CALLAS. IEEE Trans. Very Large Scale Integr. Syst. 1 (3) (1993)
Reinaldo A. Bergamaschi, Raul Camposano, Michael Payer
Allocation algorithms based on path analysis. Integr. 13 (3) (1992)
Jörg Biesenack, Norbert Wehn, A. Stoll, Michael Payer
Data Part Optimizations in the CALLAS Synthesis Environment. Synthesis for Control Dominated Circuits (1992)
Reinaldo A. Bergamaschi, Raul Camposano, Michael Payer
Scheduling under resource constraints and module assignment. Integr. 12 (1) (1991)
Reinaldo A. Bergamaschi, Raul Camposano, Michael Payer
Data-Path Synthesis Using Path Analysis. DAC (1991)
Reinaldo A. Bergamaschi, Raul Camposano, Michael Payer
Area and performance optimizations in path-based scheduling. EURO-DAC (1991)
Michael Payer
Partitioning and ordering of CMOS circuits for switch level analysis. Integr. 10 (2) (1991)
Michael Payer
Finite State Machine Theory as a Tool for Construction of Systolic Arrays. EUROCAST (1989)
Reinhard H. Rauscher, Peter Kückendahl, Michael Payer
A system for estimation of numerical stability for matrix operations in systolic arrays. Microprocess. Microprogramming 24 (1-5) (1988)
Michael Payer
Hierarchische Zerlegung von Graphen mit zwei ausgezeichneten Knoten mit Anwendugen bei der Synthese und Analyse von MOS-Schaltungen. GI Jahrestagung (2) (1988)
Michael Payer
Verification and validation of hierarchical CMOS gate array layouts. Microprocess. Microprogramming 21 (1-5) (1987)
Michael Payer
Systematischer Entwurf von Makroprozessoren. GI Jahrestagung (1980)

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Publication Activity (10 Years)

Michael Payer