Jörg Biesenack

Publication Activity (10 Years)

Years Active: 1991-1994
Publications (10 Years): 0

Publications

Norbert Wehn, Jörg Biesenack, Peter Duzy, T. Langmaier, Michael Münch, Michael Pilsl, Steffen Rumler
Scheduling of behavioral VHDL by retiming techniques. EURO-DAC (1994)
Jörg Biesenack, Michael Koster, Anton Langmaier, Stephane Ledeux, Sabine März, Michael Payer, Michael Pilsl, Steffen Rumler, Holger Soukup, Norbert Wehn, Peter Duzy
The Siemens high-level synthesis system CALLAS. IEEE Trans. Very Large Scale Integr. Syst. 1 (3) (1993)
A. Stoll, Jörg Biesenack, Steffen Rumler
Flexible timing specification in a VHDL synthesis subset. EURO-DAC (1992)
Jörg Biesenack, Norbert Wehn, A. Stoll, Michael Payer
Data Part Optimizations in the CALLAS Synthesis Environment. Synthesis for Control Dominated Circuits (1992)
Norbert Wehn, Jörg Biesenack, Michael Pilsl
A New Approach to Multiplexer Minimisation in the CALLAS Synthesis Environment. VLSI (1991)