Peter Duzy

Publication Activity (10 Years)

Years Active: 1990-1994
Publications (10 Years): 0

Publications

Norbert Wehn, Jörg Biesenack, Peter Duzy, T. Langmaier, Michael Münch, Michael Pilsl, Steffen Rumler
Scheduling of behavioral VHDL by retiming techniques. EURO-DAC (1994)
Jörg Biesenack, Michael Koster, Anton Langmaier, Stephane Ledeux, Sabine März, Michael Payer, Michael Pilsl, Steffen Rumler, Holger Soukup, Norbert Wehn, Peter Duzy
The Siemens high-level synthesis system CALLAS. IEEE Trans. Very Large Scale Integr. Syst. 1 (3) (1993)
Peter Windirsch, Peter Duzy
The CALLAS synthesis system and its application to mechatronic ASIC design problems. EURO-DAC (1993)
A. Stoll, Peter Duzy
High-Level Synthesis from VHDL with Exact Timing Constraints. DAC (1992)
Michael Koster, Martin Geiger, Peter Duzy
ASIC design using the high-level synthesis system CALLAS: a case study. ICCD (1990)