A. Stoll

Publication Activity (10 Years)

Years Active: 1992-1992
Publications (10 Years): 0

Publications

A. Stoll, Jörg Biesenack, Steffen Rumler
Flexible timing specification in a VHDL synthesis subset. EURO-DAC (1992)
A. Stoll, Peter Duzy
High-Level Synthesis from VHDL with Exact Timing Constraints. DAC (1992)
Jörg Biesenack, Norbert Wehn, A. Stoll, Michael Payer
Data Part Optimizations in the CALLAS Synthesis Environment. Synthesis for Control Dominated Circuits (1992)