Helmut E. Graeb

Publication Activity (10 Years)

Years Active: 1991-2022
Publications (10 Years): 8

Top Topics

Predicting Future

Wavelet Packet Transform

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Inga Abel, Maximilian Neuner, Helmut E. Graeb
A Hierarchical Performance Equation Library for Basic Op-Amp Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (7) (2022)
Ye X. Ding, Florin Burcea, Husni M. Habal, Helmut E. Graeb
PASTEL: Parasitic Matching-Driven Placement and Routing of Capacitor Arrays With Generalized Ratios in Charge-Redistribution SAR-ADCs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (7) (2020)
Nai-Chen Chen, Pang-Yen Chou, Helmut E. Graeb, Mark Po-Hung Lin
High-density MOM capacitor array with novel mortise-tenon structure for low-power SAR ADC. DATE (2017)
Mark Po-Hung Lin, Po-Hsun Chang, Shuenn-Yuh Lee, Helmut E. Graeb
DeMixGen: Deterministic Mixed-Signal Layout Generation With Separated Analog and Digital Signal Paths. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35 (8) (2016)
Florin Burcea, Husni M. Habal, Helmut E. Graeb
A New Chessboard Placement and Sizing Method for Capacitors in a Charge-Scaling DAC by Worst-Case Analysis of Nonlinearity. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35 (9) (2016)
Florin Burcea, Husni M. Habal, Helmut E. Graeb
Procedural capacitor placement in differential charge-scaling converters by nonlinearity analysis. DAC (2016)
Michael Zwerger, Helmut E. Graeb
Detection of asymmetric aging-critical voltage conditions in analog power-down mode. DATE (2015)
Michael Zwerger, Maximilian Neuner, Helmut E. Graeb
Power-Down Circuit Synthesis for Analog/Mixed-Signal. ICCAD (2015)
Veit Kleeberger, Helmut E. Graeb, Ulf Schlichtmann
Predicting future product performance: modeling and evaluation of standard cells in FinFET technologies. DAC (2013)
Husni M. Habal, Helmut E. Graeb
Evaluating analog circuit performance in light of MOSFET aging at different time scales. ICICDT (2013)
Michael Pehl, Helmut E. Graeb
Tolerance Design of Analog Circuits using a Branch-and-Bound Based Approach. J. Circuits Syst. Comput. 21 (8) (2012)
Michael Eick, Helmut E. Graeb
MARS: Matching-Driven Analog Sizing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31 (8) (2012)
Michael Eick, Martin Strasser, Kun Lu, Ulf Schlichtmann, Helmut E. Graeb
Comprehensive Generation of Hierarchical Placement Rules for Analog Integrated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (2) (2011)
Michael Eick, Martin Strasser, Helmut E. Graeb, Ulf Schlichtmann
Automatic generation of hierarchical placement rules for analog integrated circuits. ISPD (2010)
Michael Pehl, Michael Zwerger, Helmut E. Graeb
Sizing analog circuits using an SQP and Branch and Bound based approach. ICECS (2010)
Daniel Mueller-Gritschneder, Helmut E. Graeb, Ulf Schlichtmann
A Successive Approach to Compute the Bounded Pareto Front of Practical Multiobjective Optimization Problems. SIAM J. Optim. 20 (2) (2009)
Tobias Massier, Helmut E. Graeb, Ulf Schlichtmann
The Sizing Rules Method for CMOS and Bipolar Analog Integrated Circuit Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (12) (2008)
David M. Binkley, Helmut E. Graeb, Georges G. E. Gielen, Jaijeet S. Roychowdhury
From Transistor to PLL - Analogue Design and EDA Methods. DATE (2008)
Michael Pehl, Tobias Massier, Helmut E. Graeb, Ulf Schlichtmann
A random and pseudo-gradient approach for analog circuit sizing with non-uniformly discretized parameters. ICCD (2008)
Tobias Massier, Helmut E. Graeb, Ulf Schlichtmann
Sizing Rules for Bipolar Analog Circuit Design. DATE (2008)
Daniel Mueller, Helmut E. Graeb, Ulf Schlichtmann
Trade-off design of analog circuits using goal attainment and "Wave Front" sequential quadratic programming. DATE (2007)
Guido Stehr, Helmut E. Graeb, Kurt Antreich
Analog Performance Space Exploration by Normal-Boundary Intersection and by Fourier-Motzkin Elimination. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (10) (2007)
Jun Zou, Daniel Mueller, Helmut E. Graeb, Ulf Schlichtmann
Pareto-Front Computation and Automatic Sizing of CPPLLs. ISQED (2007)
Jun Zou, Daniel Mueller, Helmut E. Graeb, Ulf Schlichtmann
A CPPLL hierarchical optimization methodology considering jitter, power and locking time. DAC (2006)
Daniel Mueller, Guido Stehr, Helmut E. Graeb, Ulf Schlichtmann
Fast evaluation of analog circuit structures by polytopal approximations. ISCAS (2006)
Daniel Mueller, Guido Stehr, Helmut E. Graeb, Ulf Schlichtmann
Eigenschaftsraumexploration bei der hierarchischen Dimensionierung analoger integrierter Schaltungen. GI Jahrestagung (1) (2005)
Daniel Mueller, Guido Stehr, Helmut E. Graeb, Ulf Schlichtmann
Deterministic approaches to analog performance space exploration (PSE). DAC (2005)
Guido Stehr, Helmut E. Graeb, Kurt Antreich
Analog performance space exploration by Fourier-Motzkin elimination with application to hierarchical sizing. ICCAD (2004)
Guido Stehr, Helmut E. Graeb, Kurt Antreich
Performance trade-off analysis of analog circuits by normal-boundary intersection. DAC (2003)
Guido Stehr, Michael Pronath, Frank Schenkel, Helmut E. Graeb, Kurt Antreich
Initial Sizing of Analog Integrated Circuits by Centering Within Topology-Given Implicit Specification. ICCAD (2003)
Robert Schwencker, Frank Schenkel, Michael Pronath, Helmut E. Graeb
Analog Circuit Sizing Using Adaptive Worst-Case Parameter Sets. DATE (2002)
Michael Pronath, Helmut E. Graeb, Kurt Antreich
A Test Design Method for Floating Gate Defects (FGD) in Analog Integrated Circuits. DATE (2002)
Frank Schenkel, Michael Pronath, Stephan Zizala, Robert Schwencker, Helmut E. Graeb, Kurt Antreich
Mismatch Analysis and Direct Yield Optimization by Spec-Wise Linearization and Feasibility-Guided Search. DAC (2001)
Helmut E. Graeb, Stephan Zizala, Josef Eckmüller, Kurt Antreich
The Sizing Rules Method for Analog Integrated Circuit Design. ICCAD (2001)
Michael Pronath, Volker Gloeckel, Helmut E. Graeb
A Parametric Test Method for Analog Components in Integrated Mixed-Signal Circuits. ICCAD (2000)
Robert Schwencker, Frank Schenkel, Helmut E. Graeb, Kurt Antreich
The Generalized Boundary Curve-A Common Method for Automatic Nominal Design and Design Centering of Analog Circuits. DATE (2000)
Robert Schwencker, Josef Eckmüller, Helmut E. Graeb, Kurt Antreich
Automating the Sizing of Analog CMOS Circuits by Consideration of Structural Constraints. DATE (1999)
Walter M. Lindermeir, Helmut E. Graeb, Kurt Antreich
Analog testing by characteristic observation inference. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18 (9) (1999)
Josef Eckmüller, Martin Groepl, Helmut E. Graeb
Hierarchical Characterization of Analog Integrated CMOS Circuits. DATE (1998)
Walter M. Lindermeir, Thomas J. Vogels, Helmut E. Graeb
Analog Test Design with IDD Measurements for the Detection of Parametric and Catastrophic Faults. DATE (1998)
Walter M. Lindermeir, Helmut E. Graeb, Kurt Antreich
Design based analog testing by Characteristic Observation Inference. ICCAD (1995)
Kurt Antreich, Helmut E. Graeb, Claudia U. Wieser
Circuit analysis and optimization driven by worst-case distances. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13 (1) (1994)
Wolfgang T. Eisenmann, Helmut E. Graeb
Fast transient power and noise estimation for VLSI circuits. ICCAD (1994)
Helmut E. Graeb, Claudia U. Wieser, Kurt Antreich
Improved Methods for Worst-Case Analysis and Optimization Incorporating Operating Tolerances. DAC (1993)
Helmut E. Graeb, Claudia U. Wieser, Kurt Antreich
Design verification considering manufacturing tolerances by using worst-caste distances. EURO-DAC (1992)
Helmut E. Graeb, Reiner E. Lederle
Circuit yield optimization by analyzing performance statistics. Microprocess. Microprogramming 35 (1-5) (1992)
Kurt Antreich, Helmut E. Graeb
Circuit Optimization Driven by Worst-Case Distances. ICCAD (1991)