Ginés Doménech-Asensi

Publication Activity (10 Years)

Years Active: 2003-2024
Publications (10 Years): 19

Top Topics

Image Filtering

Top Venues

J. Real Time Image Process.

Publications

José Ángel Díaz-Madrid, Ginés Doménech-Asensi, Ramón Ruiz Merino, Juan Zapata-Pérez
A real-time and energy-efficient SRAM with mixed-signal in-memory computing near CMOS sensors. J. Real Time Image Process. 21 (4) (2024)
Ginés Doménech-Asensi, Ramón Ruiz Merino, Juan Zapata-Pérez, José Ángel Díaz-Madrid
A 12T SRAM in-Memory Computing differential current architecture for CNN implementations. ISCAS (2023)
Ginés Doménech-Asensi, María-Dolores Cano, Víctor Morales-Esteras
On the Use of Bayesian Networks for Real-Time Urban Traffic Measurements: a Case Study with Low-Cost Devices. J. Signal Process. Syst. 94 (3) (2022)
Pablo Rubio-Ibáñez, J. Javier Martínez-Álvarez, Ginés Doménech-Asensi
A library-based tool to translate high level DNN models into hierarchical VHDL descriptions. DCIS (2021)
José Ángel Díaz-Madrid, Ginés Doménech-Asensi, J. Javier Martínez-Álvarez, Juan Zapata-Pérez, Ramón Ruiz Merino
Joint Implementation of the Sharing OTA and Bias Current Regulation Techniques in an 11-Bit 10 MS/s Pipelined ADC. Circuits Syst. Signal Process. 40 (2) (2021)
Ginés Doménech-Asensi, Tom J. Kazmierski
Stability and Efficiency of Explicit Integration in Interconnect Analysis on GPUs. ISCAS (2020)
Ginés Doménech-Asensi, Juan Zapata-Pérez, Ramón Ruiz Merino, José-Alejandro López Alcantud, José Ángel Díaz-Madrid, Víctor Manuel Brea Sánchez, Paula López
All-hardware SIFT implementation for real-time VGA images feature extraction. J. Real Time Image Process. 17 (2) (2020)
José Ángel Díaz-Madrid, Ginés Doménech-Asensi, Ramón Ruiz Merino, Juan Zapata-Pérez, José Javier Martínez
Mixed Signal Multiply and Adder Parallel Circuit for Deep Learning Convolution Operations. ISCAS (2020)
Ginés Doménech-Asensi, Tom J. Kazmierski
High-speed analog simulation of CMOS vision chips using explicit integration techniques on many-core processors. DATE (2020)
Ginés Doménech-Asensi, Tom J. Kazmierski
An Efficient Numerical Solution Technique for VLSI Interconnect Equations on Many-Core Processors. ISCAS (2019)
Pablo Rubio-Ibáñez, J. Javier Martínez-Álvarez, Ginés Doménech-Asensi
Efficient VHDL Implementation of an Upscaling Function for Real Time Video Applications. ISCAS (2019)
Ginés Doménech-Asensi, Tom J. Kazmierski
Simulation Acceleration of Image Filtering on CMOS Vision Chips Using Many-Core Processors. FDL (2019)
Pablo Rubio-Ibáñez, J. Javier Martínez-Álvarez, Ginés Doménech-Asensi
FPGA real time synthesis of simplified SIFT algorithm. ICDSC (2018)
Juan Francisco Inglés-Romero, Ginés Doménech-Asensi, M. D. Cano-Baños, V. Morales-Esteras
Traffic Metrics at Urban Intersections using a Low-Cost Image Processing Approach. ICDSC (2018)
Ricardo Carmona-Galán, Jorge Fernández-Berni, Ángel Rodríguez-Vázquez, Paula López Martinez, Víctor Manuel Brea Sánchez, Diego Cabello Ferrer, Ginés Doménech-Asensi, Ramón Ruiz Merino, Juan Zapata-Pérez
Results of 'iCaveats', a Project on the Integration of Architectures and Components for Embedded Vision. ICDSC (2018)
Pablo Rubio-Ibáñez, Ramón Ruiz Merino, Ginés Doménech-Asensi, J. Javier Martínez-Álvarez, Juan Zapata-Pérez, José Ángel Díaz-Madrid, José-Alejandro López Alcantud
An all-hardware implementation of the subpixel refinement stage in SIFT algorithm. Int. J. Circuit Theory Appl. 46 (9) (2018)
Ginés Doménech-Asensi, Tom J. Kazmierski
Generation of new power processing structures exploiting genetic programming. ISIE (2017)
José Ángel Díaz-Madrid, Ginés Doménech-Asensi, José-Alejandro López Alcantud, M. Oberst
An 11-bit 20-MSample/s pipelined ADC with OTA bias current regulation to optimize power dissipation. ISCAS (2017)
Ramon Sanchez-Iborra, Juan F. Inglés-Romero, Ginés Doménech-Asensi, José-Luis Moreno-Cegarra, Maria-Dolores Cano
Proactive Intelligent System for Optimizing Traffic Signaling. DASC/PiCom/DataCom/CyberSciTech (2016)
Julio Illade-Quinteiro, Víctor M. Brea, Paula López Martinez, Diego Cabello, Ginés Doménech-Asensi
Distance Measurement Error in Time-of-Flight Sensors Due to Shot Noise. Sensors 15 (3) (2015)
Pablo Leyva, Ginés Doménech-Asensi, F. Javier Garrigós, Julio Illade-Quinteiro, Víctor M. Brea, Paula López, Diego Cabello
Simplification and hardware implementation of the feature descriptor vector calculation in the SIFT algorithm. FPL (2014)
Ginés Doménech-Asensi, José Ángel Díaz-Madrid, Ramón Ruiz Merino
Synthesis of CMOS analog circuit VHDL-AMS descriptions using parameterizable macromodels. Int. J. Circuit Theory Appl. 41 (7) (2013)
Víctor M. Brea, Manuel Suarez, J. Illade-Quinteiro, Paula López, Diego Cabello, Ginés Doménech-Asensi
Voltage boosters for on-chip solar cells on focal-plane processors. ICECS (2013)
Ginés Doménech-Asensi, F. Martinez-Viviente, J. Illade-Quinteiro, Juan Zapata-Pérez, Ramón Ruiz Merino, José-Alejandro López Alcantud, Juan Martínez-Alajarín, Francisco J. Fernández-Luque, Juan M. Carrillo, Miguel Angel Domínguez
A fourth order CMOS band pass filter for PIR sensors. ICECS (2012)
Maria-Dolores Cano, Ginés Doménech-Asensi
A secure energy-efficient m-banking application for mobile devices. J. Syst. Softw. 84 (11) (2011)
José Ángel Díaz-Madrid, Juan Hinojosa, Ginés Doménech-Asensi
Fuzzy logic technique for accurate analog circuits macromodel sizing. Int. J. Circuit Theory Appl. 38 (3) (2010)
José Ángel Díaz-Madrid, Harald Neubauer, Hans Hauer, Ginés Doménech-Asensi, Ramón Ruiz Merino
Power reduction of a 12-bit 40-MS/s pipeline ADC exploiting partial amplifier sharing. DATE (2009)
Ginés Doménech-Asensi, Juan Hinojosa, Ramón Ruiz Merino, José Ángel Díaz-Madrid
Accurate and reusable macromodeling technique using a fuzzy-logic approach. ISCAS (2008)
Ginés Doménech-Asensi, Juan Hinojosa, Juan Martínez-Alajarín
A behavioral model development methodology for microwave components and integration in VHDL-AMS. Microelectron. J. 38 (4-5) (2007)
Juan Hinojosa, Ginés Doménech-Asensi
Multiple adaptive neuro-fuzzy inference systems for accurate microwave CAD applications. ECCTD (2007)
José Ángel Díaz-Madrid, Pedro Monsalve-Campillo, Juan Hinojosa, María Victoria Rodellar Biarge, Ginés Doménech-Asensi
Improvement of ANNs Performance to Generate Fitting Surfaces for Analog CMOS Circuits. IWINAC (2) (2007)
Ginés Doménech-Asensi, Juan Martínez-Alajarín, Ramón Ruiz Merino, José-Alejandro López Alcantud
Synthesis on FPAA of a Smart Sthetoscope Analog Subsystem. FPL (2006)
Ginés Doménech-Asensi, José-Alejandro López Alcantud, Ramón Ruiz Merino
Description and Simulation of Bio-inspired Systems Using VHDL-AMS. IWINAC (2) (2005)
Ginés Doménech-Asensi, Ramón Ruiz Merino, Hans Hauer, José Ángel Díaz-Madrid
Current Mode CMOS Synthesis of a Motor-Control Neural System. IWANN (2) (2003)