José Ángel Díaz-Madrid

Publication Activity (10 Years)

Years Active: 2003-2024
Publications (10 Years): 7

Top Topics

Random Access Memory

Hardware Architectures

Power Dissipation

Top Venues

J. Real Time Image Process.

Int. J. Circuit Theory Appl.

Circuits Syst. Signal Process.

Publications

José Ángel Díaz-Madrid, Ginés Doménech-Asensi, Ramón Ruiz Merino, Juan Zapata-Pérez
A real-time and energy-efficient SRAM with mixed-signal in-memory computing near CMOS sensors. J. Real Time Image Process. 21 (4) (2024)
Ginés Doménech-Asensi, Ramón Ruiz Merino, Juan Zapata-Pérez, José Ángel Díaz-Madrid
A 12T SRAM in-Memory Computing differential current architecture for CNN implementations. ISCAS (2023)
José Ángel Díaz-Madrid, Ginés Doménech-Asensi, J. Javier Martínez-Álvarez, Juan Zapata-Pérez, Ramón Ruiz Merino
Joint Implementation of the Sharing OTA and Bias Current Regulation Techniques in an 11-Bit 10 MS/s Pipelined ADC. Circuits Syst. Signal Process. 40 (2) (2021)
Ginés Doménech-Asensi, Juan Zapata-Pérez, Ramón Ruiz Merino, José-Alejandro López Alcantud, José Ángel Díaz-Madrid, Víctor Manuel Brea Sánchez, Paula López
All-hardware SIFT implementation for real-time VGA images feature extraction. J. Real Time Image Process. 17 (2) (2020)
José Ángel Díaz-Madrid, Ginés Doménech-Asensi, Ramón Ruiz Merino, Juan Zapata-Pérez, José Javier Martínez
Mixed Signal Multiply and Adder Parallel Circuit for Deep Learning Convolution Operations. ISCAS (2020)
Pablo Rubio-Ibáñez, Ramón Ruiz Merino, Ginés Doménech-Asensi, J. Javier Martínez-Álvarez, Juan Zapata-Pérez, José Ángel Díaz-Madrid, José-Alejandro López Alcantud
An all-hardware implementation of the subpixel refinement stage in SIFT algorithm. Int. J. Circuit Theory Appl. 46 (9) (2018)
José Ángel Díaz-Madrid, Ginés Doménech-Asensi, José-Alejandro López Alcantud, M. Oberst
An 11-bit 20-MSample/s pipelined ADC with OTA bias current regulation to optimize power dissipation. ISCAS (2017)
Ginés Doménech-Asensi, José Ángel Díaz-Madrid, Ramón Ruiz Merino
Synthesis of CMOS analog circuit VHDL-AMS descriptions using parameterizable macromodels. Int. J. Circuit Theory Appl. 41 (7) (2013)
José Ángel Díaz-Madrid, Juan Hinojosa, Ginés Doménech-Asensi
Fuzzy logic technique for accurate analog circuits macromodel sizing. Int. J. Circuit Theory Appl. 38 (3) (2010)
José Ángel Díaz-Madrid, Harald Neubauer, Hans Hauer, Ginés Doménech-Asensi, Ramón Ruiz Merino
Power reduction of a 12-bit 40-MS/s pipeline ADC exploiting partial amplifier sharing. DATE (2009)
Ginés Doménech-Asensi, Juan Hinojosa, Ramón Ruiz Merino, José Ángel Díaz-Madrid
Accurate and reusable macromodeling technique using a fuzzy-logic approach. ISCAS (2008)
José Ángel Díaz-Madrid, Pedro Monsalve-Campillo, Juan Hinojosa, María Victoria Rodellar Biarge, Ginés Doménech-Asensi
Improvement of ANNs Performance to Generate Fitting Surfaces for Analog CMOS Circuits. IWINAC (2) (2007)
Ginés Doménech-Asensi, Ramón Ruiz Merino, Hans Hauer, José Ángel Díaz-Madrid
Current Mode CMOS Synthesis of a Motor-Control Neural System. IWANN (2) (2003)
José-Alejandro López Alcantud, José Ángel Díaz-Madrid, Hans Hauer, Ramón Ruiz Merino
An Analogue Current-Mode Hardware Design Proposal for Preprocessing Layers in ART-Based Neural Networks. IWANN (2) (2003)