José-Alejandro López Alcantud

Publication Activity (10 Years)

Years Active: 2000-2020
Publications (10 Years): 3

Top Topics

Image Binarization

Image Processing Algorithms

Top Venues

Int. J. Circuit Theory Appl.

J. Real Time Image Process.

Publications

Ginés Doménech-Asensi, Juan Zapata-Pérez, Ramón Ruiz Merino, José-Alejandro López Alcantud, José Ángel Díaz-Madrid, Víctor Manuel Brea Sánchez, Paula López
All-hardware SIFT implementation for real-time VGA images feature extraction. J. Real Time Image Process. 17 (2) (2020)
Pablo Rubio-Ibáñez, Ramón Ruiz Merino, Ginés Doménech-Asensi, J. Javier Martínez-Álvarez, Juan Zapata-Pérez, José Ángel Díaz-Madrid, José-Alejandro López Alcantud
An all-hardware implementation of the subpixel refinement stage in SIFT algorithm. Int. J. Circuit Theory Appl. 46 (9) (2018)
José Ángel Díaz-Madrid, Ginés Doménech-Asensi, José-Alejandro López Alcantud, M. Oberst
An 11-bit 20-MSample/s pipelined ADC with OTA bias current regulation to optimize power dissipation. ISCAS (2017)
Ginés Doménech-Asensi, F. Martinez-Viviente, J. Illade-Quinteiro, Juan Zapata-Pérez, Ramón Ruiz Merino, José-Alejandro López Alcantud, Juan Martínez-Alajarín, Francisco J. Fernández-Luque, Juan M. Carrillo, Miguel Angel Domínguez
A fourth order CMOS band pass filter for PIR sensors. ICECS (2012)
Ginés Doménech-Asensi, Juan Martínez-Alajarín, Ramón Ruiz Merino, José-Alejandro López Alcantud
Synthesis on FPAA of a Smart Sthetoscope Analog Subsystem. FPL (2006)
Ginés Doménech-Asensi, José-Alejandro López Alcantud, Ramón Ruiz Merino
Description and Simulation of Bio-inspired Systems Using VHDL-AMS. IWINAC (2) (2005)
José-Alejandro López Alcantud, José Ángel Díaz-Madrid, Hans Hauer, Ramón Ruiz Merino
An Analogue Current-Mode Hardware Design Proposal for Preprocessing Layers in ART-Based Neural Networks. IWANN (2) (2003)
José-Alejandro López Alcantud, Tom Kazmierski
VHDL-AMS modeling of self-organizing neural systems. ISCAS (2000)