An all-hardware implementation of the subpixel refinement stage in SIFT algorithm.
Pablo Rubio-IbáñezRamón Ruiz MerinoGinés Doménech-AsensiJ. Javier Martínez-ÁlvarezJuan Zapata-PérezJosé Ángel Díaz-MadridJosé-Alejandro López AlcantudPublished in: Int. J. Circuit Theory Appl. (2018)
Keyphrases
- hardware implementation
- learning algorithm
- optimal solution
- software implementation
- image processing algorithms
- euler number
- fpga implementation
- detection algorithm
- computational complexity
- objective function
- dynamic programming
- image binarization
- pipeline architecture
- signal processing
- hardware architecture
- k means
- fpga technology