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Power reduction of a 12-bit 40-MS/s pipeline ADC exploiting partial amplifier sharing.
José Ángel Díaz-Madrid
Harald Neubauer
Hans Hauer
Ginés Doménech-Asensi
Ramón Ruiz Merino
Published in:
DATE (2009)
Keyphrases
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power reduction
power consumption
low power
analog to digital converter
power saving
wide dynamic range
dynamic range
multithreading
computer simulation
parallel computing