Dilip K. Banerji

Publication Activity (10 Years)

Years Active: 1969-2009
Publications (10 Years): 0

Publications

Shawki Areibi, X. Bao, Gary Gréwal, Dilip K. Banerji, Peng Du
Meta-Heuristic Based Techniques for FPGA Placement: A Study. Int. J. Comput. Their Appl. 16 (1) (2009)
Ming Xu, Gary Gréwal, Shawki Areibi, Charlie Obimbo, Dilip K. Banerji
Near-linear wirelength estimation for FPGA placement. CCECE (2009)
Gary Gréwal, Stelian Coros, Dilip K. Banerji, Andrew Morton
Assigning data to dual memory banks in DSPs with a genetic algorithm using a repair heuristic. Appl. Intell. 26 (1) (2007)
Gary Gréwal, Stelian Coros, Dilip K. Banerji, Andrew Morton
Comparing a Genetic Algorithm Penalty Function and Repair Heuristic in the DSP Application Domain. Artificial Intelligence and Applications (2006)
Shouvik Chowdhury, Gary William Grewal, Dilip K. Banerji
Clustering Hanan Points to Reduce Vlsi Interconnect Routing Times. CCECE (2006)
Gary Gréwal, Stelian Coros, Dilip K. Banerji, Andrew Morton, Mario Ventresca
Optimized Memory Assignment for DSPs. IEEE Congress on Evolutionary Computation (2006)
Peng Du, Gary William Grewal, Shawki Areibi, Dilip K. Banerji
A Fast Hierarchical Approach to FPGA Placement. ESA/VLSI (2004)
Gary William Grewal, Thomas Charles Wilson, Ming Xu, Dilip K. Banerji
Shrubbery: A New Algorithm for Quickly Growing High-Quality Steiner Trees. VLSI Design (2004)
Zhibin Dai, Dilip K. Banerji
Routability Prediction for Field Programmable Gate Arrays with a Routing Hierarchy. VLSI Design (2003)
Wei Li, Dilip K. Banerji
Routability Prediction for Hierarchical FPGAs. Great Lakes Symposium on VLSI (1999)
Anupam Basu, Dilip K. Banerji, Amit Basu, Thomas Charles Wilson, Jayanti C. Majithia
A Modified Approach to Test Plan Generation for Combinational Logic Blocks. VLSI Design 4 (3) (1996)
J. Shu, Thomas Charles Wilson, Dilip K. Banerji
Instruction-Set Matching and GA-based Selection for Embedded-Processor Code Generation. VLSI Design (1996)
Thomas Charles Wilson, Nilanjan Mukherjee, Manoj K. Garg, Dilip K. Banerji
An ILP Solution for Optimum Scheduling, Module and Register Allocation, and Operation Binding in Datapath Synthesis. VLSI Design 3 (1) (1995)
Thomas Charles Wilson, Gary William Grewal, Dilip K. Banerji
An ILP Solution for Simultaneous Scheduling, Allocation, and Binding in Multiple Block Synthesis. ICCD (1994)
Thomas Charles Wilson, Gary Gréwal, Ben Halley, Dilip K. Banerji
An integrated approach to retargetable code generation. HLSS (1994)
Thomas Charles Wilson, Gary William Grewal, Shawn Henshall, Dilip K. Banerji
An ILP-based approach to code generation. Code Generation for Embedded Processors (1994)
Thomas Charles Wilson, Nilanjan Mukherjee, Manoj K. Garg, Dilip K. Banerji
An Integrated and Accelerated ILP Solution for Scheduling, Module Allocation, and Binding in Datapath Synthesis. VLSI Design (1993)
Thomas Charles Wilson, Manoj K. Garg, R. Deadman, Ben Halley, Dilip K. Banerji
MinMux: a new approach for global minimization of multiplexers in interconnect synthesis. Great Lakes Symposium on VLSI (1993)
Anupam Basu, Thomas Charles Wilson, Dilip K. Banerji, Jayanti C. Majithia
An Approach to Minimize Testability Overhead for BILBO based Built-In-Self-Test. VLSI Design (1992)
Thomas Charles Wilson, Anupam Basu, Dilip K. Banerji, Jayanti C. Majithia
Test plan generation and concurrent scheduling of tests in the presence of conflicts. Great Lakes Symposium on VLSI (1991)
Anupam Basu, Thomas Charles Wilson, Dilip K. Banerji, Jayanti C. Majithia
Integrated approach to area-time tradeoff for built-in-self-test in VLSI circuits. Great Lakes Symposium on VLSI (1991)
M. Balakrishnan, Arun K. Majumdar, Dilip K. Banerji, James G. Linders, Jayanti C. Majithia
Allocation of multiport memories in data path synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7 (4) (1988)
M. Balakrishnan, Arun K. Majumdar, Dilip K. Banerji, James G. Linders
Synthesis of decentralised controllers from high level description. Microprocess. Microprogramming 22 (3) (1988)
M. Balakrishnan, S. Sutarwala, Arun K. Majumdar, Dilip K. Banerji, James G. Linders
A Semantic Approach for Modular Synthesis of VLSI Systems. Inf. Process. Lett. 27 (1) (1988)
Dilip K. Banerji, Saroj Kaushik
Representation and processing of fractions in a residue system. IEEE Symposium on Computer Arithmetic (1983)
Jacques Raymond, Dilip K. Banerji
Using a Microprocessor in an Intelligent Graphics Terminal. Computer 9 (4) (1976)
Dilip K. Banerji
A Novel Implementation Method for Addition and Subtraction in Residue Number Systems. IEEE Trans. Computers 23 (1) (1974)
S. R. Das, Dilip K. Banerji, A. Chattopadhyay
On Control Memory Minimization in Microprogrammed Digital Computers. IEEE Trans. Computers 22 (9) (1973)
Dilip K. Banerji, Janusz A. Brzozowski
On Translation Algorithms in Residue Number Systems. IEEE Trans. Computers 21 (12) (1972)
Dilip K. Banerji, Janusz A. Brzozowski
Sign Detection in Residue Number Systems. IEEE Trans. Computers 18 (4) (1969)