Thomas Charles Wilson

Publication Activity (10 Years)

Years Active: 1991-2004
Publications (10 Years): 0

Publications

Gary William Grewal, Thomas Charles Wilson, Ming Xu, Dilip K. Banerji
Shrubbery: A New Algorithm for Quickly Growing High-Quality Steiner Trees. VLSI Design (2004)
Gary William Grewal, Thomas Charles Wilson
Mapping Reference Code to Irregular DSPS within the Retargetable, Optimizing Compiler Cogen(T). Int. J. Comput. Intell. Appl. 3 (1) (2003)
Gary Gréwal, Thomas Charles Wilson, Andrew Morton
An EGA approach to the compile-time assignment of data to multiple memories in digital-signal processors. SIGARCH Comput. Archit. News 31 (1) (2003)
Gary William Grewal, Thomas Charles Wilson, Christopher W. Nell
An Enhanced Genetic Algorithm Approach to the Channel Assignment Problem in Mobile Cellular Networks. Canadian Conference on AI (2002)
Gary William Grewal, Thomas Charles Wilson
An Enhanced Genetic Algorithm for Solving the High-Level Synthesis Problems of Scheduling, Allocation, and Binding. Int. J. Comput. Intell. Appl. 1 (1) (2001)
Gary William Grewal, Thomas Charles Wilson
Mapping reference code to irregular DSPs within the retargetable, optimizing compiler COGEN(T). MICRO (2001)
Gary William Grewal, Thomas Charles Wilson
An Enhanced Genetic Solution for Scheduling, Module Allocation, and Binding in VLSI Design. VLSI Design (1997)
Thomas Charles Wilson, Gary William Grewal
Shake And Bake: A Method of Mapping Code to Irregular DSPs. VLSI Design (1997)
Anupam Basu, Dilip K. Banerji, Amit Basu, Thomas Charles Wilson, Jayanti C. Majithia
A Modified Approach to Test Plan Generation for Combinational Logic Blocks. VLSI Design 4 (3) (1996)
J. Shu, Thomas Charles Wilson, Dilip K. Banerji
Instruction-Set Matching and GA-based Selection for Embedded-Processor Code Generation. VLSI Design (1996)
Thomas Charles Wilson, Nilanjan Mukherjee, Manoj K. Garg, Dilip K. Banerji
An ILP Solution for Optimum Scheduling, Module and Register Allocation, and Operation Binding in Datapath Synthesis. VLSI Design 3 (1) (1995)
Thomas Charles Wilson, Gary William Grewal, Dilip K. Banerji
An ILP Solution for Simultaneous Scheduling, Allocation, and Binding in Multiple Block Synthesis. ICCD (1994)
Thomas Charles Wilson, Gary Gréwal, Ben Halley, Dilip K. Banerji
An integrated approach to retargetable code generation. HLSS (1994)
Thomas Charles Wilson, Gary William Grewal, Shawn Henshall, Dilip K. Banerji
An ILP-based approach to code generation. Code Generation for Embedded Processors (1994)
Thomas Charles Wilson, Nilanjan Mukherjee, Manoj K. Garg, Dilip K. Banerji
An Integrated and Accelerated ILP Solution for Scheduling, Module Allocation, and Binding in Datapath Synthesis. VLSI Design (1993)
Thomas Charles Wilson, Manoj K. Garg, R. Deadman, Ben Halley, Dilip K. Banerji
MinMux: a new approach for global minimization of multiplexers in interconnect synthesis. Great Lakes Symposium on VLSI (1993)
Anupam Basu, Thomas Charles Wilson, Dilip K. Banerji, Jayanti C. Majithia
An Approach to Minimize Testability Overhead for BILBO based Built-In-Self-Test. VLSI Design (1992)
Thomas Charles Wilson, Anupam Basu, Dilip K. Banerji, Jayanti C. Majithia
Test plan generation and concurrent scheduling of tests in the presence of conflicts. Great Lakes Symposium on VLSI (1991)
Anupam Basu, Thomas Charles Wilson, Dilip K. Banerji, Jayanti C. Majithia
Integrated approach to area-time tradeoff for built-in-self-test in VLSI circuits. Great Lakes Symposium on VLSI (1991)