Cherrice Traver

Publication Activity (10 Years)

Years Active: 1993-2005
Publications (10 Years): 0

Publications

Robert B. Reese, Mitchell A. Thornton, Cherrice Traver, David Hemmendinger
Early evaluation for performance enhancement in phased logic. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24 (4) (2005)
Robert B. Reese, Mitchell A. Thornton, Cherrice Traver
A Coarse-Grain Phased Logic CPU. IEEE Trans. Computers 54 (7) (2005)
Kenneth Fazel, Lun Li, Mitchell A. Thornton, Robert B. Reese, Cherrice Traver
Performance enhancement in phased logic circuits using automatic slack-matching buffer insertion. ACM Great Lakes Symposium on VLSI (2004)
Robert B. Reese, Mitchell A. Thornton, Cherrice Traver
A Coarse-Grain Phased Logic CPU. ASYNC (2003)
Robert B. Reese, Mitchell A. Thornton, Cherrice Traver
A Fine-Grain Phased Logic CPU. ISVLSI (2003)
Mitchell A. Thornton, Kenneth Fazel, Robert B. Reese, Cherrice Traver
Generalized Early Evaluation in Self-Timed Circuits. DATE (2002)
Robert B. Reese, Mitchell A. Thornton, Cherrice Traver
Arithmetic Logic Circuits Using Self-Timed Bit Level Dataflow and Early Evaluation. ICCD (2001)
Abdülkadir Erden, Aydan M. Erkmen, Ismet Erkmen, Ronald B. Bucinell, Cherrice Traver, Leila Notash
The multidisciplinary international virtual design studio (MIVDS). IEEE Trans. Educ. 43 (3) (2000)
K. W. Hsu, Cherrice Traver
Guest Editorial Introduction to the Special Issue on the 1995 IEEE ASIC Conference. IEEE Trans. Very Large Scale Integr. Syst. 4 (3) (1996)
Garth Baulch, David Hemmendinger, Cherrice Traver
Analyzing and verifying locally clocked circuits with the concurrency workbench. Great Lakes Symposium on VLSI (1995)
Richard Auletta, Robert B. Reese, Cherrice Traver
A Comparison of Synchronous and Asynchronous FSMD Designs. ICCD (1993)
Richard Auletta, Cherrice Traver
Rapid-prototyping of high-assurance systems. Great Lakes Symposium on VLSI (1993)