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Performance enhancement in phased logic circuits using automatic slack-matching buffer insertion.
Kenneth Fazel
Lun Li
Mitchell A. Thornton
Robert B. Reese
Cherrice Traver
Published in:
ACM Great Lakes Symposium on VLSI (2004)
Keyphrases
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logic circuits
low power
matching algorithm
pattern matching
computer vision
loss function
image enhancement
image processing
gate array
pattern recognition
high speed
image matching
functional decomposition
tunnel diode
multistage
efficient implementation