Charles H. Stapper

Publication Activity (10 Years)

Years Active: 1976-2000
Publications (10 Years): 0

Publications

Charles H. Stapper
LSI yield modeling and process monitoring. IBM J. Res. Dev. 44 (1) (2000)
Wayne F. Ellis, John E. Barth Jr., Sri Divakaruni, Jeffrey H. Dreibelbis, Anatol Furman, Erik L. Hedberg, Hsing-San Lee, Thomas M. Maffitt, Christopher P. Miller, Charles H. Stapper, Howard L. Kalter
Multipurpose DRAM architecture for optimal power, performance, and product flexibility. IBM J. Res. Dev. 39 (1-2) (1995)
Charles H. Stapper, A. J. Rideout
On Fractal Yield Models: A Statistical Paradox. DFT (1994)
Israel Koren, Zahava Koren, Charles H. Stapper
A statistical study of defect maps of large area VLSI IC's. IEEE Trans. Very Large Scale Integr. Syst. 2 (2) (1994)
Charles H. Stapper, J. A. Patrick, R. J. Rosner
Yield Model for ASIC and Processor Chips. DFT (1993)
Charles H. Stapper
Improved Yield Models for Fault-Tolerant Memory Chips. IEEE Trans. Computers 42 (7) (1993)
Israel Koren, Zahava Koren, Charles H. Stapper
A Unified Negative-Binomial Distribution for Yield Analysis of Defect-Tolerant Circuits. IEEE Trans. Computers 42 (6) (1993)
Charles H. Stapper, Hsing-San Lee
Synergistic Fault-Tolerance for Memory Chips. IEEE Trans. Computers 41 (9) (1992)
Charles H. Stapper
A New Statistical Approach for Fault-Tolerant VLSI Systems. FTCS (1992)
Charles H. Stapper
Statistics associated with spatial fault simulation used for evaluating integrated circuit yield enhancement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10 (3) (1991)
Charles H. Stapper
Large-Area Fault Clusters and Fault Tolerance in VLSI Circuits: A Review. IBM J. Res. Dev. 33 (2) (1989)
Charles H. Stapper
Simulation of spatial fault distributions for integrated circuit yield estimations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8 (12) (1989)
Andrzej J. Strojwas, Clark Beck, Dennis Buss, Tülin Erdim Mangir, Charles H. Stapper
Yield of VLSI circuits: myths vs. reality (panel). DAC (1986)
Charles H. Stapper
Yield Model for Fault Clusters Within Integrated Circuits. IBM J. Res. Dev. 28 (5) (1984)
Charles H. Stapper
Modeling of Defects in Integrated Circuit Photolithographic Patterns. IBM J. Res. Dev. 28 (4) (1984)
Charles H. Stapper
Modeling of Integrated Circuit Defect Sensitivities. IBM J. Res. Dev. 27 (6) (1983)
Charles H. Stapper, A. N. McLaren, M. Dreckmann
Yield Model for Productivity Optimization of VLSI Memory Chips with Redundancy and Partially Good Product. IBM J. Res. Dev. 24 (3) (1980)
Charles H. Stapper
LSI Yield Modeling and Process Monitoring. IBM J. Res. Dev. 20 (3) (1976)