C. W. Liu

Publication Activity (10 Years)

Years Active: 2014-2023
Publications (10 Years): 10

Top Topics

Mobility Patterns

Room Temperature

Quantum Computing

Top Venues

VLSI Technology and Circuits

Publications

Jih-Chao Chiu, Eknath Sarkar, Yuan-Ming Liu, Yu-Ciao Chen, Yu-Cheng Fan, C. W. Liu
μA/μm, DIBL =44mV/V, Positive VT, and Process Temp. of 300 °C. VLSI Technology and Circuits (2023)
Zefu Zhao, Yu-Rui Chen, Yun-Wen Chen, Wan-Hsuan Hsieh, Jer-Fu Wang, Jia-Yang Lee, Yifan Xing, Guan-Hua Chen, C. W. Liu
-Si/Ge Substrates Achieving Record 2Pr = 84 μC/cm² and Endurance > 1E11. VLSI Technology and Circuits (2023)
K.-Y. Hsiang, J.-Y. Lee, F.-S. Chang, Z.-F. Lou, Z.-X. Li, Z.-H. Li, J.-H. Chen, C. W. Liu, T.-H. Hou, Min-Hung Lee
FeRAM Recovery up to 200 Periods with Accumulated Endurance 1012 Cycles and an Applicable Array Circuit toward Unlimited eNVM Operations. VLSI Technology and Circuits (2023)
Yi-Chun Liu, Yu-Rui Chen, Yun-Wen Chen, Hsin-Cheng Lin, Wan-Hsuan Hsieh, Chien-Te Tu, Bo-Wei Huang, Wei-Jen Chen, Chun-Yi Cheng, Shee-Jier Chueh, C. W. Liu
Extremely High-κ Hf0.2Zr0.8O2 Gate Stacks Integrated into Ge0.95Si0.05 Nanowire and Nanosheet nFETs Featuring Respective Record Ion per Footprint of 9200μA/μm and Record Ion per Stack of 360μA at VOV=VDS=0.5V. VLSI Technology and Circuits (2023)
K.-Y. Hsiang, J.-Y. Lee, Z.-F. Lou, F.-S. Chang, Z.-X. Li, C. W. Liu, T.-H. Hou, P. Su, M. H. Lee
Cryogenic Endurance of Anti-ferroelectric and Ferroelectric $\text{Hf}_{1-\mathrm{x}}\text{Zr}_{\mathrm{X}}\mathrm{O}_{2}$ for Quantum Computing Applications. IRPS (2023)
J.-Y. Lee, F.-S. Chang, K.-Y. Hsiang, P.-H. Chen, Z.-F. Luo, Z.-X. Li, J.-H. Tsai, C. W. Liu, Min-Hung Lee
3D Stackable Vertical Ferroelectric Tunneling Junction (V-FTJ) with on/off Ratio 1500x, Applicable Cell Current, Self-Rectifying Ratio 1000x, Robust Endurance of 10⁹ Cycles, Multilevel and Demonstrated Macro Operation Toward High-Density BEOL NVMs. VLSI Technology and Circuits (2023)
Yu-Rui Chen, Yi-Chun Liu, Zefu Zhao, Wan-Hsuan Hsieh, Jia-Yang Lee, Chien-Te Tu, Bo-Wei Huang, Jer-Fu Wang, Shee-Jier Chueh, Yifan Xing, Guan-Hua Chen, Hung-Chun Chou, Dong Soo Woo, M. H. Lee, C. W. Liu
First Stacked Nanosheet FeFET Featuring Memory Window of 1.8V at Record Low Write Voltage of 2V and Endurance >1E11 Cycles. VLSI Technology and Circuits (2023)
H.-L. Chiang, J.-F. Wang, K.-H. Lin, C.-H. Nien, J.-J. Wu, K.-Y. Hsiang, C.-P. Chuu, Y.-W. Chen, X. W. Zhang, C. W. Liu, Tahui Wang, C. C. Wang, M.-H. Lee, M.-F. Chang, C.-S. Chang, T. C. Chen
Interfacial-Layer Design for Hf1-xZrxO2-Based FTJ Devices: From Atom to Array. VLSI Technology and Circuits (2022)
Chung-En Tsai, Chun-Yi Cheng, Bo-Wei Huang, Hsin-Cheng Lin, Tao Chou, Chien-Te Tu, Yi-Chun Liu, Sun-Rong Jan, Yu-Rui Chen, Wan-Hsuan Hsieh, Kung-Ying Chiu, Shee-Jier Chueh, C. W. Liu
Nearly Ideal Subthreshold Swing and Delay Reduction of Stacked Nanosheets Using Ultrathin Bodies. VLSI Technology and Circuits (2022)
Chia-Chun Yen, An-Hung Tai, Yu-Chieh Liu, Chun-Hung Yeh, C. W. Liu
Mobility Enhancement and Reliability Characterization of Back-Channel-Etch Amorphous InGaZnO TFT with Double Layers. DRC (2020)
C. W. Liu, X. X. Jin, L. S. Li
A web services-based multidisciplinary design optimization framework for complex engineering systems with uncertainties. Comput. Ind. 65 (4) (2014)