Albrecht P. Stroele

Publication Activity (10 Years)

Years Active: 1990-2001
Publications (10 Years): 0

Publications

Tobias Schüle, Albrecht P. Stroele
Scheduling tests for low power built-in self-test. ISCAS (5) (2001)
Tobias Schüle, Albrecht P. Stroele
Test Scheduling for Minimal Energy Consumption under Power Constraints. VTS (2001)
Albrecht P. Stroele
Synthesis for Arithmetic Built-In Self-Tes. VTS (2000)
Albrecht P. Stroele, Steffen Tarnick
Embedded Checker Architectures for Cyclic and Low-Cost Arithmetic Codes. J. Electron. Test. 16 (4) (2000)
Albrecht P. Stroele
Synthesizing data paths with arithmetic self-test. ISCAS (2000)
Frank Mayer, Albrecht P. Stroele
A Versatile BIST Technique Combining Test Registers and Accumulators. VLSI Design (2000)
Albrecht P. Stroele, Steffen Tarnick
Programmable Embedded Self-Testing Checkers for All-Unidirectional Error-Detecting Code. VTS (1999)
Albrecht P. Stroele
Signature Analysis for Test Responses of Sequential Circuits. VLSI Design 1999 (2) (1999)
Albrecht P. Stroele, Frank Mayer
Test Scheduling with Loop Folding and Its Application to Test Configurations with Accumulators. Asian Test Symposium (1999)
Gerald Spiegel, Albrecht P. Stroele
Realistic Fault Modeling and Extraction of Multiple Bridging and Break Faults. VLSI Design 1998 (2) (1998)
Frank Mayer, Albrecht P. Stroele
Configuring Arithmetic Pattern Generators and Response Compactors from the RT-Modules of a Circuit. Asian Test Symposium (1998)
Albrecht P. Stroele
Bit Serial Pattern Generation and Response Compaction Using Arithmetic Functions. VTS (1998)
Steffen Tarnick, Albrecht P. Stroele
Embedded self-testing checkers for low-cost arithmetic codes. ITC (1998)
Albrecht P. Stroele, Hans-Joachim Wunderlich
Hardware-optimal test register insertion. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17 (6) (1998)
Albrecht P. Stroele, Frank Mayer
Methods to reduce test application time for accumulator-based self-test. VTS (1997)
Albrecht P. Stroele
BIST Pattern Generators Using Addition and Subtraction Operations. J. Electron. Test. 11 (1) (1997)
Albrecht P. Stroele
Test response compaction using arithmetic functions. VTS (1996)
Albrecht P. Stroele
Arithmetic Pattern Generators for Built-In Self-Test. ICCD (1996)
Albrecht P. Stroele, Hans-Joachim Wunderlich
Test register insertion with minimum hardware cost. ICCAD (1995)
Albrecht P. Stroele
A Self-Test Approach Using Accumulators as Test Pattern Generators. ISCAS (1995)
Gerald Spiegel, Albrecht P. Stroele
A unified approach to the extraction of realistic multiple bridging and break faults. EURO-DAC (1995)
Albrecht P. Stroele
Signature analysis and aliasing for sequential circuits. VTS (1995)
Albrecht P. Stroele, Hans-Joachim Wunderlich
Configuring Flip-Flops to BIST Registers. ITC (1994)
Albrecht P. Stroele
Signature Analysis for Sequential Circuits with Reset. EDAC-ETC-EUROASIC (1994)
Albrecht P. Stroele
Partitioning and hierarchical description of self-testable designs. VLSI (1993)
Albrecht P. Stroele
Self-Test Scheduling with Bounded Test Execution. ITC (1992)
Albrecht P. Stroele, Hans-Joachim Wunderlich
Signature Analysis and Test Scheduling for Self-Testable Circuits. FTCS (1991)
Albrecht P. Stroele, Hans-Joachim Wunderlich
Error masking in self-testable circuits. ITC (1990)