1Mbit 1T1C 3D DRAM with Monolithically Stacked One Planar FET and Two Vertical FET Heterogeneous Oxide Semiconductor layers over Si CMOS.
Y. OkamotoY. KomuraT. MizuguchiT. SaitoM. ItoK. KimuraTatsuya OnukiYoshinori AndoH. SawaiT. MurakawaH. KunitakeTakanori MatsuzakiH. KimuraM. FujitaM. IkedaShunpei YamazakiPublished in: VLSI Technology and Circuits (2023)