Tri-Scan: A Novel DFT Technique for CMOS Path Delay Fault Testing.
Ramyanshu DattaRavi GuptaAntony SebastineJacob A. AbrahamManuel A. d'AbreuPublished in: ITC (2004)
Keyphrases
- high speed
- fault model
- discrete fourier transform
- fourier transform
- shortest path
- frequency domain
- power consumption
- low cost
- fault diagnosis
- fault injection
- optimal path
- path length
- test cases
- low power
- destination node
- circuit design
- power supply
- vlsi circuits
- real time embedded systems
- failure modes
- software testing
- test suite
- discrete cosine transform
- fault detection