A systematic approach to synthesis of verification test-suites for modular SoC designs.
Sudhakar SurendranRubin A. ParekhjiR. GovindarajanPublished in: SoCC (2008)
Keyphrases
- test suite
- model checker
- test cases
- test suite reduction
- model checking
- regression testing
- test generation
- test case generation
- formal verification
- formal methods
- static analysis
- software testing
- testing process
- application specific integrated circuits
- design space exploration
- java programs
- low power
- temporal logic
- tool support
- description language
- texture synthesis
- hardware and software
- low cost
- set theory
- embedded systems
- test data
- knowledge based systems
- multi agent systems
- number of test cases
- learning algorithm
- data sets