Yehua Ling

Publication Activity (10 Years)

Years Active: 2020-2023
Publications (10 Years): 10

Top Topics

Stereo Matching

Stereo Matching Algorithm

Image Stabilization

Top Venues

J. Syst. Archit.

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Rihui Song, Zhidong Tan, Hongli Liang, Yehua Ling, Gang Chen, Kai Huang, Jin Gong
Dense Depth Estimation for Monocular Endoscope Robot with an Adaptive Baseline. SMC (2023)
Yuanxing Yan, Yehua Ling, Kai Huang, Gang Chen
An efficient real-time accelerator for high-accuracy DNN-based optical flow estimation in FPGA. J. Syst. Archit. 136 (2023)
Rihui Song, Silu Guo, Ni Liu, Yehua Ling, Jin Gong, Kai Huang
Real-Time Instance Segmentation and Tip Detection for Neuroendoscopic Surgical Instruments. ICONIP (10) (2023)
Yu Zhang, Yi Zheng, Yehua Ling, Haitao Meng, Gang Chen
A robust and real-time DNN-based multi-baseline stereo accelerator in FPGAs. J. Syst. Archit. 143 (2023)
Fangzhou Zhang, Mingyue Cui, Jiakang Zhang, Yehua Ling, Han Liu, Kai Huang
Accelerated Optimization for Simulation of Brain Spiking Neural Network on GPGPUs. ICA3PP (6) (2023)
Yehua Ling, Tao He, Yu Zhang, Haitao Meng, Kai Huang, Gang Chen
Lite-Stereo: A Resource-Efficient Hardware Accelerator for Real-Time High-Quality Stereo Estimation Using Binary Neural Network. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (12) (2022)
Yehua Ling, Yuanxing Yan, Kai Huang, Gang Chen
FlowAcc: Real-Time High-Accuracy DNN-based Optical Flow Accelerator in FPGA. DATE (2022)
Yehua Ling, Yuanxing Yan, Kai Huang, Gang Chen
Ultra-Flow: An Ultra-fast and High-quality Optical Flow Accelerator with Deep Feature Matching on FPGA. FPL (2022)
Yehua Ling, Tao He, Haitao Meng, Yu Zhang, Gang Chen
Hardware accelerator for an accurate local stereo matching algorithm using binary neural network. J. Syst. Archit. 117 (2021)
Gang Chen, Yehua Ling, Tao He, Haitao Meng, Shengyu He, Yu Zhang, Kai Huang
StereoEngine: An FPGA-Based Accelerator for Real-Time High-Quality Stereo Estimation With Binary Neural Network. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (11) (2020)