Yavar Safaei Mehrabani

Publication Activity (10 Years)

Years Active: 2013-2024
Publications (10 Years): 12

Top Topics

Image Processing

Electron Microscopy

Top Venues

Int. J. High Perform. Syst. Archit.

Circuits Syst. Signal Process.

J. Circuits Syst. Comput.

Int. J. Inf. Comput. Secur.

Publications

Yavar Safaei Mehrabani, Reza Faghih Mirzaee
DAFA: Dynamic approximate full adders for high area and energy efficiency. Integr. 97 (2024)
Yavar Safaei Mehrabani, Samaneh Goldani Gigasari, Mohammad Mirzaei, Hamidreza Uoosefian
A Novel Highly-Efficient Inexact Full Adder Cell for Motion and Edge Detection Systems of Image Processing in CNFET Technology. ACM J. Emerg. Technol. Comput. Syst. 18 (4) (2022)
Akram Mohammadi, Mokhtar Mohammadi Ghanatghestani, Amir Sabbagh Molahosseini, Yavar Safaei Mehrabani
Image processing with high-speed and low-energy approximate arithmetic circuit. Sustain. Comput. Informatics Syst. 36 (2022)
Yavar Safaei Mehrabani, Roghayeh Ataie, Mohammad Hossein Shafiabadi, Abolghasem Ghasempour
Design and implementation of an ASIP for SHA-3 hash algorithm. Int. J. Inf. Comput. Secur. 17 (3/4) (2022)
Zahra Zareei, Mehdi Bagherizadeh, Mohammad Hossein Shafiabadi, Yavar Safaei Mehrabani
Design of efficient approximate 1-bit Full Adder cells using CNFET technology applicable in motion detector systems. Microelectron. J. 108 (2021)
Yavar Safaei Mehrabani, Mohammad Hossein Shafiabadi
A novel high-performance and reliable multi-threshold CNFET full adder cell design. Int. J. High Perform. Syst. Archit. 7 (1) (2017)
Yavar Safaei Mehrabani, Reza Faghih Mirzaee, Zahra Zareei, Seyedeh Mohtaram Daryabari
A Novel High-Speed, Low-Power CNTFET-Based Inexact Full Adder Cell for Image Processing Application of Motion Detector. J. Circuits Syst. Comput. 26 (5) (2017)
Yavar Safaei Mehrabani, Mohammad Eshghi
Noise and Process Variation Tolerant, Low-Power, High-Speed, and Low-Energy Full Adders in CNFET Technology. IEEE Trans. Very Large Scale Integr. Syst. 24 (11) (2016)
Yavar Safaei Mehrabani, Mohammad Eshghi
A Symmetric, Multi-Threshold, High-Speed and Efficient-Energy 1-Bit Full Adder Cell Design Using CNFET Technology. Circuits Syst. Signal Process. 34 (3) (2015)
Yavar Safaei Mehrabani, Reza Faghih Mirzaee, Mohammad Eshghi
A novel low-energy CNFET-based full adder cell using pass-transistor logic. Int. J. High Perform. Syst. Archit. 5 (4) (2015)
Yavar Safaei Mehrabani, Mohammad Eshghi
Erratum to: A Symmetric, Multi-Threshold, High-Speed and Efficient-Energy 1-Bit Full Adder Cell Design Using CNFET Technology. Circuits Syst. Signal Process. 34 (3) (2015)
Yavar Safaei Mehrabani, Mohammad Eshghi
High-Speed, High-Frequency and Low-PDP, CNFET Full Adder Cells. J. Circuits Syst. Comput. 24 (9) (2015)
Yavar Safaei Mehrabani, Zahra Zareei, Ahmad Khademzadeh
A high-speed and high-performance full adder cell based on 32-nm CNFET technology for low voltages. Int. J. High Perform. Syst. Archit. 4 (4) (2013)