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Erratum to: A Symmetric, Multi-Threshold, High-Speed and Efficient-Energy 1-Bit Full Adder Cell Design Using CNFET Technology.
Yavar Safaei Mehrabani
Mohammad Eshghi
Published in:
Circuits Syst. Signal Process. (2015)
Keyphrases
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high speed
cost effective
case study
design process
neural network
energy minimization
information technology
computer systems
design principles
enabling technology
participatory design
bit vector