Yanbin Jiang

Publication Activity (10 Years)

Years Active: 1997-2024
Publications (10 Years): 10

Top Topics

Artificial Bee Colony

Trust Propagation

Social Recommendation

Top Venues

Frontiers Comput. Sci.

Publications

Yanbin Jiang, Huifang Ma, Xiaohui Zhang, Zhixin Li, Liang Chang
Incorporating metapath interaction on heterogeneous information network for social recommendation. Frontiers Comput. Sci. 18 (1) (2024)
Yuhang Liu, Huifang Ma, Yanbin Jiang, Zhixin Li
Modelling risk and return awareness for p2p lending recommendation with graph convolutional networks. Appl. Intell. 52 (5) (2022)
Qingqing Li, Huifang Ma, Ju Li, Zhixin Li, Yanbin Jiang
Searching Target Communities with Outliers in attributed graph. Knowl. Based Syst. 235 (2022)
Yanbin Jiang, Huifang Ma, Xiaohui Zhang, Zhixin Li, Liang Chang
An Effective Two-way Metapath Encoder over Heterogeneous Information Network for Recommendation. ICMR (2022)
Yuhang Liu, Huifang Ma, Yanbin Jiang, Zhixin Li
Learning to recommend via random walk with profile of loan and lender in P2P lending. Expert Syst. Appl. 174 (2021)
Yanbin Jiang, Huifang Ma, Yuhang Liu, Zhixin Li
Attentional Social Recommendation System with Graph Convolutional Network. IJCNN (2021)
Yanbin Jiang, Huifang Ma, Yuhang Liu, Zhixin Li, Liang Chang
Enhancing social recommendation via two-level graph attentional networks. Neurocomputing 449 (2021)
Yuhang Liu, Huifang Ma, Yanbin Jiang, Zhixin Li
Top-N Recommendation in P2P Lending: A Hybrid Graph Ranking Using Investor Profile. ICONIP (2) (2020)
Yanbin Jiang, Huifang Ma, Yuhang Liu, Zhixin Li
Exploring User Trust and Reliability for Recommendation: A Hypergraph Ranking Approach. ICONIP (2) (2020)
Yanbin Jiang, Pengyu Zhou, Rongxin Zhan, Xiang Li, Dongni Li
An artificial bee colony with self-adaptive operators and alterable search depth approach for intercell scheduling. CEC (2016)
Yanbin Jiang, Sachin S. Sapatnekar, Cyrus Bamji
Technology mapping for high-performance static CMOS and pass transistor logic designs. IEEE Trans. Very Large Scale Integr. Syst. 9 (5) (2001)
Yanbin Jiang, Sachin S. Sapatnekar
An integrated algorithm for combined placement and libraryless technology mapping. ICCAD (1999)
Yanbin Jiang, Sachin S. Sapatnekar, Cyrus Bamji, Juho Kim
Combined transistor sizing with buffer insertion for timing optimization. CICC (1998)
Yanbin Jiang, Sachin S. Sapatnekar, Cyrus Bamji
A fast global gate collapsing technique for high performance designs using static CMOS and pass transistor logic. ICCD (1998)
Yanbin Jiang, Sachin S. Sapatnekar, Cyrus Bamji, Juho Kim
Interleaving buffer insertion and transistor sizing into a single optimization. IEEE Trans. Very Large Scale Integr. Syst. 6 (4) (1998)
Juho Kim, Cyrus Bamji, Yanbin Jiang, Sachin S. Sapatnekar
Concurrent transistor sizing and buffer insertion by considering cost-delay tradeoffs. ISPD (1997)