Yajuan He

Publication Activity (10 Years)

Years Active: 2005-2024
Publications (10 Years): 27

Top Topics

Write Operations

Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

Publications

Wei He, Puvi Bai, Hongyang Luo, Zhenghao Jin, Han Wu, Junyi Zhang, Xingchen Chao, Haiqi Liu, Yajuan He, Qiang Li
131TOPS/W 8b ACIM Exploiting Weight-Embedded Auto-Accumulation and Supporting Symmetric Quantization Networks. CICC (2024)
Zilin Wang, Hongyang Luo, ZeYang Peng, Xingchen Chao, Yajuan He
An 8T SRAM Based Digital Compute-In-Memory Macro For Multiply-And-Accumulate Accelerating. ISCAS (2023)
Hao Chen, Shenhao Jiang, Shaowei Zhen, Yajuan He, Hailiang Xiong, Xin Chen, Hongyang Wu, Liang Huang, Yongsheng Du, Bo Zhang
A Fast-Transient Right-Half-Plane Zero-Free Hybrid Buck-Boost Converter. ASICON (2023)
Feiyu Zhu, Shaowei Zhen, Xilin Yi, Haoran Pei, Bowen Hou, Yajuan He
Design of Approximate Radix-256 Booth Encoding for Error-Tolerant Computing. IEEE Trans. Circuits Syst. II Express Briefs 69 (4) (2022)
Xin Si, Yung-Ning Tu, Wei-Hsing Huang, Jian-Wei Su, Pei-Jung Lu, Jing-Hong Wang, Ta-Wei Liu, Ssu-Yen Wu, Ruhui Liu, Yen-Chi Chou, Yen-Lin Chung, William Shih, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Nan-Chun Lien, Wei-Chiang Shih, Yajuan He, Qiang Li, Meng-Fan Chang
A Local Computing Cell and 6T SRAM-Based Computing-in-Memory Macro With 8-b MAC Operation for Edge AI Chips. IEEE J. Solid State Circuits 56 (9) (2021)
Yuxin Zhang, Sitao Zeng, Zhiguo Zhu, Zhaolong Qin, Chen Wang, Jingjing Li, Sanfeng Zhang, Yajuan He, Chunmeng Dou, Xin Si, Meng-Fan Chang, Qiang Li
A 40nm 1Mb 35.6 TOPS/W MLC NOR-Flash Based Computation-in-Memory Structure for Machine Learning. ISCAS (2021)
Lulin Cai, Yiduan Qian, Yajuan He, Wen Feng
Design of Approximate Multiplierless DCT with CSD Encoding for Image Processing. ISCAS (2021)
Yajuan He, Ziji Zhang, Xiong Zhou, Qiang Li
Teaching Logic and Sequential Cell Characterization in Digital Integrated Circuits. ICETT (2021)
Haoran Pei, Xilin Yi, Hang Zhou, Yajuan He
Design of Ultra-Low Power Consumption Approximate 4-2 Compressors Based on the Compensation Characteristic. IEEE Trans. Circuits Syst. II Express Briefs 68 (1) (2021)
Ziji Zhang, Yajuan He, Bo Zhang
A Time-Efficient Automatic Circuit Approximation Method. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2020)
Xin Si, Yung-Ning Tu, Wei-Hsing Huang, Jian-Wei Su, Pei-Jung Lu, Jing-Hong Wang, Ta-Wei Liu, Ssu-Yen Wu, Ruhui Liu, Yen-Chi Chou, Zhixiao Zhang, Syuan-Hao Sie, Wei-Chen Wei, Yun-Chen Lo, Tai-Hsing Wen, Tzu-Hsiang Hsu, Yen-Kai Chen, William Shih, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Nan-Chun Lien, Wei-Chiang Shih, Yajuan He, Qiang Li, Meng-Fan Chang
15.5 A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips. ISSCC (2020)
Yajuan He, Xilin Yi, Ziji Zhang, Bin Ma, Qiang Li
A Probabilistic Prediction-Based Fixed-Width Booth Multiplier for Approximate Computing. IEEE Trans. Circuits Syst. (12) (2020)
Xilin Yi, Haoran Pei, Zijie Zhang, Hang Zhou, Yajuan He
Design of an Energy-Efficient Approximate Compressor for Error-Resilient Multiplications. ISCAS (2019)
Yajuan He, Jiubai Zhang, Xiaoqing Wu, Xin Si, Shaowei Zhen, Bo Zhang
A Half-Select Disturb-Free 11T SRAM Cell With Built-In Write/Read-Assist Scheme for Ultralow-Voltage Operations. IEEE Trans. Very Large Scale Integr. Syst. 27 (10) (2019)
Jiubai Zhang, Xiaoqing Wu, Xilin Yi, Jiaxun Lv, Yajuan He
A Subthreshold 10T SRAM Cell with Enhanced Read and Write Operations. ISCAS (2019)
Ziji Zhang, Yajuan He, Jin He, Xilin Yi, Qiang Li, Bo Zhang
Optimal Slope Ranking: An Approximate Computing Approach for Circuit Pruning. ISCAS (2018)
Zijie Zhang, Yajuan He
A Low-Error Energy-Efficient Fixed-Width Booth Multiplier With Sign-Digit-Based Conditional Probability Estimation. IEEE Trans. Circuits Syst. II Express Briefs (2) (2018)
Yan Xing, Ziji Zhang, Yiduan Qian, Qiang Li, Yajuan He
An Energy-Efficient Approximate DCT for Wireless Capsule Endoscopy Application. ISCAS (2018)
Jiubai Zhang, Yajuan He, Xiaoqing Wu, Bo Zhang
A Disturb-Free 10T SRAM Cell with High Read Stability and Write Ability for Ultra-Low Voltage Operations. APCCAS (2018)
Yajuan He, Xilin Yi, Bin Ma, Zijie Zhang, Bo Zhang
A Probabilistic Prediction Based Fixed-Width Booth Multiplier. APCCAS (2018)
Jiajia Wang, Shaowei Zhen, Yajuan He, Penghao Zeng, Jiawei Chen, Wanli Zhou, Ping Luo, Bo Zhang
Digital PID Based on Pseudo Type-III Compensation for DC-DC Converter. APCCAS (2018)
Zengxin Liu, Shaowei Zhen, Shuiqing Xi, Xinjiang Gao, Lei Yang, Jiongwei Zheng, He Tang, Yajuan He, Ping Luo, Bo Zhang
A digital-assistant time-to-amplitude converter with dynamic range improvement. ASICON (2017)
Shangjie Ma, Zhiyuan Pei, Yajuan He
Study on Simulation of Rice Yield with WOFOST in Heilongjiang Province. CCTA (2016)
Shangjie Ma, Zhiyuan Pei, Yajuan He, Lianlin Wang, Zhiping Ma
Simulation of Winter Wheat Yield with WOFOST in County Scale. CCTA (1) (2015)
Quan Wu, Li Sun, Yajuan He, Fei Wang, Danqiong Wang, Weijie Jiao, Haijun Wang, Xue Han
The Methodology of Monitoring Crops with Remote Sensing at the National Scale. CCTA (1) (2015)
Dongjun Wang, Ping Luo, Qing Hua, Shaowei Zhen, Yajuan He
A pulse skipping modulation with adaptive duty ratio in buck converter application. IEICE Electron. Express 12 (17) (2015)
Yajuan He, Ziji Zhang, Bin Ma, Jinpeng Li, Shaowei Zhen, Ping Luo, Qiang Li
A fast and energy efficient binary-to-pseudo CSD converter. ISCAS (2015)
Quan Wu, Hualang Hu, Yanxia Liu, Danqiong Wang, Xinyu Duan, Lijuan Jia, Yajuan He
Study on Survey Methods for Crop Area Change Reasons at National Scale. CCTA (2014)
Kun Ao, Yajuan He, Liang Li, Yuxin Wang, Qiang Li
A 14-bit 100MS/s pipelined A/D converter with 2b interstage redundancy. ISIC (2014)
Yajuan He, Song Wang, Qi Ling, Qiang Li
A digital calibration technique for multi-bit-per-stage pipelined ADC. ISIC (2014)
Shaowei Zhen, Xiaohui Zhu, Ping Luo, Yajuan He, Bo Zhang
Digital Error Corrector for Phase Lead-Compensated Buck Converter in DVS Applications. IEEE Trans. Very Large Scale Integr. Syst. 21 (9) (2013)
Yajuan He, Bo Chen, Qiang Li
Blind-LMS based digital background calibration for a 14-Bit 200-MS/s pipelined ADC. VLSI-SoC (2013)
Yajuan He, Chip-Hong Chang
-Bit Multiplier Design. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2009)
Yajuan He, Chip-Hong Chang
A Power-Delay Efficient Hybrid Carry-Lookahead/Carry-Select Based Redundant Binary to Two's Complement Converter. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2008)
Yajuan He, Chip-Hong Chang
A low-power, high-speed RB-to-NB converter for fast redundant binary multiplier. ISCAS (2006)
Yajuan He, Chip-Hong Chang, Jiangmin Gu, Hossam A. H. Fahmy
A novel covalent redundant binary Booth encoder. ISCAS (1) (2005)
Yajuan He, Chip-Hong Chang, Jiangmin Gu
An area efficient 64-bit square root carry-select adder for low power applications. ISCAS (4) (2005)