An area efficient 64-bit square root carry-select adder for low power applications.

Yajuan He Chip-Hong Chang Jiangmin Gu

Published in: ISCAS (4) (2005)

Keyphrases

low power
square root
power consumption
low cost
logic circuits
high speed
low power consumption
digital signal processing
image sensor
power dissipation
computational complexity
floating point
arrival rate
mixed signal