Will R. Moore

Publication Activity (10 Years)

Years Active: 1986-2007
Publications (10 Years): 0

Publications

Xinyue Fan, Will R. Moore, Camelia Hora, Guido Gronthoud
Extending gate-level diagnosis tools to CMOS intra-gate faults. IET Comput. Digit. Tech. 1 (6) (2007)
Xinyue Fan, Will R. Moore, Camelia Hora, Mario Konijnenburg, Guido Gronthoud
A Gate-Level Method for Transistor-Level Bridging Fault Diagnosis. VTS (2006)
Xinyue Fan, Will R. Moore, Camelia Hora, Guido Gronthoud
Stuck-open fault diagnosis with stuck-at model. ETS (2005)
Xinyue Fan, Will R. Moore, Camelia Hora, Guido Gronthoud
A novel stuck-at based method for transistor stuck-open fault diagnosis. ITC (2005)
Will R. Moore, Guido Gronthoud, Keith Baker, Maurice Lousberg
Delay-fault testing and defects in deep sub-micron ICs-does critical resistance really mean anything? ITC (2000)
Ovidio V. Maiuri, Will R. Moore
Implications of Voltage and Dimension Scaling on CMOS Testing: The Multidimensional Testing Paradigm. VTS (1998)
William P. Marnane, Will R. Moore
Testing VLSI regular arrays. J. Electron. Test. 6 (2) (1995)
S. J. Barnfield, Will R. Moore
Multiple Fault Diagnosis in Printed Circuit Boards. ITC (1993)
Howard C. Card, Will R. Moore
. Neural Networks 3 (3) (1990)
William P. Marnane, Will R. Moore
Testing a motion estimator array. ASAP (1990)
Howard C. Card, Will R. Moore
Vlsi Devices and Circuits for Neural Networks. Int. J. Neural Syst. 1 (2) (1989)
José G. Delgado-Frias, Will R. Moore
A semantic network architecture for artificial intelligence processing. TAI (1989)
John A. Trotter, Will R. Moore
Imperfectly connected 2D arrays for image processing. FTCS (1989)
José G. Delgado-Frias, Will R. Moore
Parallel architectures for AI semantic network processing. Knowl. Based Syst. 1 (5) (1988)
William P. Marnane, Will R. Moore
Testing of VLSI regular arrays. ICCD (1988)
Will R. Moore
A review of fault-tolerant techniques for the enhancement of integrated circuit yield. Proc. IEEE 74 (5) (1986)