Vijaya Sankara Rao Pasupureddi

Publication Activity (10 Years)

Years Active: 2013-2023
Publications (10 Years): 25

Top Topics

Cmos Technology

Intestinal Motility

Compressive Sensing

Power Dissipation

Top Venues

Int. J. Circuit Theory Appl.

Publications

Prema Kumar Govindaswamy, Raviteja Kammari, Vijaya Sankara Rao Pasupureddi
An adaptive link training based hybrid circuit topology for full-duplex on-chip interconnects. Int. J. Circuit Theory Appl. 51 (8) (2023)
Prema Kumar Govindaswamy, Nijwm Wary, Vijaya Sankara Rao Pasupureddi
Power Efficient Echo-Cancellation Based Hybrid for Full-Duplex Chip-to-Chip Interconnects. ISCAS (2022)
Prema Kumar Govindaswamy, Nijwm Wary, Vijaya Sankara Rao Pasupureddi
A Low-Power Half-Rate Charge-Steering Hybrid for Full-Duplex Chip-to-Chip Interconnects. ISCAS (2022)
Prema Kumar Govindaswamy, Vijaya Sankara Rao Pasupureddi
A power-efficient current-integrating hybrid for full-duplex communication over chip-to-chip interconnects. Int. J. Circuit Theory Appl. 50 (12) (2022)
Rakesh Rena, Raviteja Kammari, Vijaya Sankara Rao Pasupureddi
Digitally Intensive Sub-sampling Mixer-First Direct Down-Conversion Receiver Architecture. MWSCAS (2022)
Rakesh Rena, Suraj Kumar Verma, Vijaya Sankara Rao Pasupureddi
A Process Scalable Architecture for Low Noise Figure Sub-Sampling Mixer-First RF Front-End. ISCAS (2021)
Prema Kumar Govindaswamy, Vijaya Sankara Rao Pasupureddi
-1, 20-Gb/s, Low-Power, Charge-Steering Half-Rate PRBS Generator in 1.2 V, 65 nm CMOS. Circuits Syst. Signal Process. 40 (11) (2021)
Pankaj Venuturupalli, Prema Kumar Govindaswamy, Vijaya Sankara Rao Pasupureddi
An Adaptive Hybrid with Residue Monitor for Full-Duplex On-Chip Interconnects. ISCAS (2020)
Pankaj Venuturupalli, Prema Kumar Govindaswamy, Vijaya Sankara Rao Pasupureddi
Residue monitor enabled charge-mode adaptive echo-cancellation for simultaneous bidirectional signaling over on-chip interconnects. Microelectron. J. 104 (2020)
Raviteja Kammari, Vijaya Sankara Rao Pasupureddi
Charge controlled delay element enabled widely linear power efficient MPCG-MDLL in 1.2V, 65nm CMOS. Int. J. Circuit Theory Appl. 48 (2) (2020)
Prema Kumar Govindaswamy, Vijaya Sankara Rao Pasupureddi
A 2^7 -1 Low-Power Half-Rate 16-Gb/s Charge-Mode PRBS Generator in 1.2V, 65nm CMOS. ISVLSI (2020)
Raviteja Kammari, Vijaya Sankara Rao Pasupureddi
A Widely Linear, Power Efficient, Charge Controlled Delay Element for Multi-phase Clock Generation in 1.2 V, 65 nm CMOS. VDAT (2019)
Ajinkya Kale, Johannes Sturm, Vijaya Sankara Rao Pasupureddi
A -40-dB EVM 20-MHz subsampling multistandard receiver architecture with dynamic carrier detection, bandwidth estimation, and EVM optimization. Int. J. Circuit Theory Appl. 47 (4) (2019)
Ajinkya Kale, Suchendranath Popuri, Michael Koeberle, Johannes Sturm, Vijaya Sankara Rao Pasupureddi
A -40 dB EVM, 77 MHz Dual-Band Tunable Gain Sub-Sampling Receiver Front End in 65-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2019)
Ajinkya Kale, Johannes Sturm, Vijaya Sankara Rao Pasupureddi
0.9 to 2.5 GHz Sub-Sampling Receiver Architecture for Dynamically Reconfigurable SDR. ISVLSI (2018)
Ajinkya Kale, Graciele Batistell, Suchendranath Popuri, Vijaya Sankara Rao Pasupureddi, Wolfgang Bösch, Johannes Sturm
Integration solutions for reconfigurable multi-standard wireless transceivers. Elektrotech. Informationstechnik 135 (1) (2018)
Divya Duvvuri, Vijaya Sankara Rao Pasupureddi
Design and analysis of a current mode integrated CTLE with charge mode adaptation. Microelectron. J. 53 (2016)
Prateek Pendyala, Vijaya Sankara Rao Pasupureddi
100-Mb/s enhanced data rate MIL-STD-1553B controller in 65-nm CMOS technology. IEEE Trans. Aerosp. Electron. Syst. 52 (6) (2016)
Divya Duvvuri, Vijaya Sankara Rao Pasupureddi
An Integrated Common Gate CTLE Receiver Front End with Charge Mode Adaptation. ISVLSI (2016)
Prateek Pendyala, Vijaya Sankara Rao Pasupureddi
Backward compatible MIL-STD-1553B analog transceiver upgrade for 100-Mb/s data rate. VDAT (2016)
Bhuvanan Kaliannan, Vijaya Sankara Rao Pasupureddi
A low power charge mode compressive acquisition of multichannel EEG signals. ISCAS (2016)
Suchendranath Popuri, Vijaya Sankara Rao Pasupureddi, Johannes Sturm
A tunable gain and tunable band active balun LNA for IEEE 802.11ac WLAN receivers. ESSCIRC (2016)
Divya Duvvuri, Somanshu Agarwal, Vijaya Sankara Rao Pasupureddi
A new hybrid circuit topology for simultaneous bidirectional signaling over on-chip interconnects. ISCAS (2016)
Prateek Pendyala, Vijaya Sankara Rao Pasupureddi
RT-MIL-STD-1553+: Remote terminal controller for MIL-STD-1553B at 100-Mb/s data rate. ISQED (2015)
Prateek Pendyala, Vijaya Sankara Rao Pasupureddi
MIL-STD-1553+: Integrated remote terminal and bus controller at 100-Mb/s data rate. ISCAS (2015)
R. Gopikrishnan, Vijaya Sankara Rao Pasupureddi, Govindarajulu Regeti
A Power Efficient Fully Differential Back Terminated Current-Mode HDMI Source. VLSI Design (2014)
Somanshu Agarwal, Vijaya Sankara Rao Pasupureddi
A 5-Gb/s adaptive CTLE with eye-monitoring for multi-drop bus applications. MWSCAS (2014)
Bhuvanan Kaliannan, Vijaya Sankara Rao Pasupureddi
A Low Power CMOS Imager Based on Distributed Compressed Sensing. VLSI Design (2014)
Mahsa Shoaran, Mariazel Maqueda Lopez, Vijaya Sankara Rao Pasupureddi, Yusuf Leblebici, Alexandre Schmid
A low-power area-efficient compressive sensing approach for multi-channel neural recording. ISCAS (2013)
Bhuvanan Kaliannan, Vijaya Sankara Rao Pasupureddi
Implementation of a Charge Redistribution Based 2-D DCT Architecture for Wireless Capsule Endoscopy. VLSI Design (2013)