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A Widely Linear, Power Efficient, Charge Controlled Delay Element for Multi-phase Clock Generation in 1.2 V, 65 nm CMOS.
Raviteja Kammari
Vijaya Sankara Rao Pasupureddi
Published in:
VDAT (2019)
Keyphrases
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power consumption
high speed
low power
power dissipation
cmos technology
power management
low cost
data sets
nm technology
real time
cost effective
training phase
power reduction