An adaptive link training based hybrid circuit topology for full-duplex on-chip interconnects.
Prema Kumar GovindaswamyRaviteja KammariVijaya Sankara Rao PasupureddiPublished in: Int. J. Circuit Theory Appl. (2023)
Keyphrases
- power dissipation
- cmos technology
- high speed
- analog vlsi
- circuit design
- power consumption
- low power
- chip design
- low cost
- evolvable hardware
- nm technology
- high density
- analog circuits
- physical design
- mixed signal
- power reduction
- digital signal processing
- digital circuits
- training set
- small world
- hardware implementation
- input output
- test set
- supervised learning