Power Efficient Echo-Cancellation Based Hybrid for Full-Duplex Chip-to-Chip Interconnects.
Prema Kumar GovindaswamyNijwm WaryVijaya Sankara Rao PasupureddiPublished in: ISCAS (2022)
Keyphrases
- power dissipation
- ibm power processor
- power consumption
- chip design
- low cost
- high speed
- high density
- analog vlsi
- programmable logic
- physical design
- single chip
- multithreading
- vlsi implementation
- circuit design
- lower cost
- cmos technology
- wireless sensor networks
- data structure
- neural network
- power management
- computationally efficient
- memory subsystem