Vacius Jusas

Publication Activity (10 Years)

Years Active: 2001-2024
Publications (10 Years): 16

Top Topics

Comprehensive Analysis

Digital Forensics

Top Venues

Inf. Technol. Control.

Comput. Sci. Inf. Syst.

Publications

Amr F. Mohamed, Vacius Jusas
Comprehensive Analysis of Feature Extraction Methods for Emotion Recognition on Motor Imagery from Multichannel EEG Recordings. WorldCIST (2) (2024)
Zeba Mahmood, Vacius Jusas
Implementation Framework for a Blockchain-Based Federated Learning Model for Classification Problems. Symmetry 13 (7) (2021)
Sandeepak Bhandari, Vacius Jusas
An Abstraction Based Approach for Reconstruction of TimeLine in Digital Forensics. Symmetry 12 (1) (2020)
Sandeepak Bhandari, Vacius Jusas
An Ontology Based on the Timeline of Log2timeline and Psort Using Abstraction Approach in Digital Forensics. Symmetry 12 (4) (2020)
Sandeepak Bhandari, Vacius Jusas
The Phases Based Approach for Regeneration of Timeline in Digital Forensics. INISTA (2020)
Vacius Jusas, Sam Gilvine Samuvel
Classification of Motor Imagery Using Combination of Feature Extraction and Reduction Methods for Brain-Computer Interface. Inf. Technol. Control. 48 (2) (2019)
Vacius Jusas, Jiaxu Zhang, Jing Li
Robust Backstepping Sliding Mode Control with L2-Gain Performance for Reference Input Wheel Slip Tracking of Vehicle. Inf. Technol. Control. 48 (4) (2019)
Vacius Jusas, Saulius Japertas, Tautvydas Baksys, Sandeepak Bhandari
Logical filter approach for early stage cyber-attack detection. Comput. Sci. Inf. Syst. 16 (2) (2019)
Tomas Uktveris, Vacius Jusas
Development of a Modular Board for EEG Signal Acquisition. Sensors 18 (7) (2018)
Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Liudas Motiejunas, Rimantas Seinauskas
Black box delay fault models for non-scan sequential circuits. Comput. Sci. Inf. Syst. 15 (1) (2018)
Algimantas Venckauskas, Vacius Jusas, Kestutis Paulikas, Jevgenijus Toldinas
Methodology to investigate BitTorrent sync protocol. Comput. Sci. Inf. Syst. 14 (1) (2017)
Tomas Uktveris, Vacius Jusas
Convolutional Neural Networks for Four-Class Motor Imagery Data Classification. IDC (2017)
Vacius Jusas, Darius Birvinskas, Elvar Gahramanov
Methods and Tools of Digital Triage in Forensic Context: Survey and Future Directions. Symmetry 9 (4) (2017)
Tomas Uktveris, Vacius Jusas
Application of Convolutional Neural Networks to Four-Class Motor Imagery Classification Problem. Inf. Technol. Control. 46 (2) (2017)
Vacius Jusas, Joaquín Nicolás Ros, Boriss Misnevs
Software Engineering Competence Remote Evaluation Process Model. Balt. J. Mod. Comput. 5 (3) (2017)
Algimantas Venckauskas, Vacius Jusas, Kestutis Paulikas, Jevgenijus Toldinas
A Methodology and Tool for Investigation of Artifacts Left by the BitTorrent Client. Symmetry 8 (6) (2016)
Darius Birvinskas, Vacius Jusas, Ignas Martisius, Robertas Damasevicius
Fast DCT algorithms for EEG data compression in embedded systems. Comput. Sci. Inf. Syst. 12 (1) (2015)
Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas
Path delay test generation at functional level. IET Comput. Digit. Tech. 9 (3) (2015)
Darius Birvinskas, Vacius Jusas
Energy Efficient Method for Motor Imagery Data Compression. ICIST (2015)
Algimantas Venckauskas, Vacius Jusas, Kestutis Paulikas, Jevgenijus Toldinas
Investigation of Artifacts Left by BitTorrent Client on the Local Computer Operating under Windows 8.1. Inf. Technol. Control. 44 (4) (2015)
Tomas Uktveris, Vacius Jusas
Comparison of Feature Extraction Methods for EEG BCI Classification. ICIST (2015)
Vacius Jusas, Tomas Neverdauskas
Stimuli generation framework for testing multiple processes in VHDL. Inf. Technol. Control. 43 (4) (2014)
Vacius Jusas, Tomas Neverdauskas
Stimuli generator for testing processes in VHDL. NORCHIP (2014)
Darius Birvinskas, Vacius Jusas, Ignas Martisius, Robertas Damasevicius
Data compression of EEG signals for artificial neural network classification. Inf. Technol. Control. 42 (3) (2013)
Vacius Jusas, Tomas Neverdauskas
Combining Software and Hardware Test Generation Methods to Verify VHDL Models. Inf. Technol. Control. 42 (4) (2013)
Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas
Functional delay test generation approach using a software prototype of the circuit. Comput. Sci. Inf. Syst. 10 (3) (2013)
Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas
Delay fault testing using partial multiple scan chains. Microelectron. Reliab. 53 (12) (2013)
Vacius Jusas, Tomas Neverdauskas
Novel Method to Generate Tests for VHDL. ICIST (2013)
Ignas Martisius, Darius Birvinskas, Robertas Damasevicius, Vacius Jusas
EEG Dataset Reduction and Classification Using Wave Atom Transform. ICANN (2013)
Darius Birvinskas, Vacius Jusas, Ignas Martisius, Robertas Damasevicius
EEG Dataset Reduction and Feature Extraction Using Discrete Cosine Transform. EMS (2012)
Vacius Jusas, Tomas Neverdauskas
FSM Based Functional Test Generation Framework for VHDL. ICIST (2012)
Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas
Evaluation of testability enhancement using software prototype. IET Comput. Digit. Tech. 6 (3) (2012)
Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas
Functional fault models for non-scan sequential circuits. Microelectron. Reliab. 51 (12) (2011)
Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas
Functional delay test generation based on software prototype. Microelectron. Reliab. 49 (12) (2009)
Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas
Development of Functional Delay Tests. DSD (2008)
Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas
Test generation at the algorithm-level for gate-level fault coverage. Microelectron. Reliab. 48 (7) (2008)
Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas
The Criteria of Functional Delay Test Quality Assessment. DSD (2007)
Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas
Functional Test Generation Based on Combined Random and Deterministic Search Methods. Informatica 18 (1) (2007)
Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas
Transition Faults Testing Based on Functional Delay Tests. DDECS (2007)
Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas
Transition Fault Test Reuse. DSD (2006)
Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas
Functional Test Generation Remote Tool. DSD (2005)
Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas
The Realization-Independent Testing Based on the Black Box Fault Models. Informatica 16 (1) (2005)
Vacius Jusas, Kestutis Paulikas, Rimantas Seinauskas
Procedures for Selection of Validation Vectors on the Algorithm Level. LATW (2001)