Rimantas Seinauskas

Publication Activity (10 Years)

Years Active: 1997-2018
Publications (10 Years): 2

Top Topics

Mutation Testing

Test Generation

Symbolic Execution

Top Venues

Comput. Sci. Inf. Syst.

IET Comput. Digit. Tech.

Microelectron. Reliab.

Publications

Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Liudas Motiejunas, Rimantas Seinauskas
Black box delay fault models for non-scan sequential circuits. Comput. Sci. Inf. Syst. 15 (1) (2018)
Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas
Path delay test generation at functional level. IET Comput. Digit. Tech. 9 (3) (2015)
Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas
Functional delay test generation approach using a software prototype of the circuit. Comput. Sci. Inf. Syst. 10 (3) (2013)
Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas
Delay fault testing using partial multiple scan chains. Microelectron. Reliab. 53 (12) (2013)
Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas
Evaluation of testability enhancement using software prototype. IET Comput. Digit. Tech. 6 (3) (2012)
Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas
Functional fault models for non-scan sequential circuits. Microelectron. Reliab. 51 (12) (2011)
Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas
Functional delay test generation based on software prototype. Microelectron. Reliab. 49 (12) (2009)
Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas
Development of Functional Delay Tests. DSD (2008)
Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas
Test generation at the algorithm-level for gate-level fault coverage. Microelectron. Reliab. 48 (7) (2008)
Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas
The Criteria of Functional Delay Test Quality Assessment. DSD (2007)
Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas
Functional Test Generation Based on Combined Random and Deterministic Search Methods. Informatica 18 (1) (2007)
Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas
Transition Faults Testing Based on Functional Delay Tests. DDECS (2007)
Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas
Transition Fault Test Reuse. DSD (2006)
Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas
Functional Test Generation Remote Tool. DSD (2005)
Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas
The Realization-Independent Testing Based on the Black Box Fault Models. Informatica 16 (1) (2005)
Eduardas Bareisa, Kestutis Motiejunas, Rimantas Seinauskas
Identifying Legal and Illegal States in Synchronous Sequential Circuits Using Test Generation. Informatica 14 (2) (2003)
Vacius Jusas, Kestutis Paulikas, Rimantas Seinauskas
Procedures for Selection of Validation Vectors on the Algorithm Level. LATW (2001)
Rimantas Seinauskas
A distance laboratory for computer-aided design. MSE (1997)