V. S. Kanchana Bhaaskaran

Publication Activity (10 Years)

Years Active: 2006-2024
Publications (10 Years): 16

Top Topics

Positive Feedback

Low Power Consumption

Top Venues

J. Circuits Syst. Comput.

Microelectron. J.

Publications

Hemavathy Sriramulu, J. Kokila, V. S. Kanchana Bhaaskaran
Adaptive PUF design to authenticate and evaluate heterogeneous IPs in edge computing. J. Supercomput. 80 (16) (2024)
Hemavathy Sriramulu, V. S. Kanchana Bhaaskaran
Arbiter PUF - A Review of Design, Composition, and Security Aspects. IEEE Access 11 (2023)
Prathiba Ashok, Suyash Vardhan Srivathshav, E. Ramkumar, P. Rajkamal, V. S. Kanchana Bhaaskaran
Lightweight VLSI Architectures for Image Encryption Applications. Int. J. Inf. Secur. Priv. 16 (1) (2022)
S. Hemavathy, V. S. Kanchana Bhaaskaran
Double Edge-Triggered Tristate Flip-Flop Physical Unclonable Function for Secure IoT Ecosystem. iSES (2021)
Bhuvana B. P., V. S. Kanchana Bhaaskaran
Analysis of FinFET-Based Adiabatic Circuits for the Design of Arithmetic Structures. J. Circuits Syst. Comput. 29 (1) (2020)
E. Ramkumar, D. Gracin, P. Rajkamal, Bhuvana B. P., V. S. Kanchana Bhaaskaran
Design and Analysis of Low Power and High Speed FinFET based Hybrid Full Adder/Subtractor Circuit (FHAS). iSES (2020)
S. Hemavathy, V. S. Kanchana Bhaaskaran
Design and Analysis of Secure Quasi-Adiabatic Tristate Physical Unclonable Function. iSES (2020)
Keshav Govindarajan, V. S. Kanchana Bhaaskaran
Borrow Select Subtractor for Low Power and Area Efficiency. ISVLSI (2020)
Bhuvana B. P., V. S. Kanchana Bhaaskaran
Design of FinFET-based Energy Efficient Pass-Transistor Adiabatic Logic for ultra-low power applications. Microelectron. J. 92 (2019)
A. Anita Angeline, V. S. Kanchana Bhaaskaran
Design impacts of delay invariant high-speed clock delayed dual keeper domino circuit. IET Circuits Devices Syst. 13 (8) (2019)
P. Sasipriya, V. S. Kanchana Bhaaskaran
Design of Low Power VLSI Circuits Using Two Phase Adiabatic Dynamic Logic (2PADL). J. Circuits Syst. Comput. 27 (4) (2018)
Bhuvana B. P., V. S. Kanchana Bhaaskaran
Positive Feedback Symmetric Adiabatic Logic Against Differential Power Attack. VLSI Design (2018)
V. S. Kanchana Bhaaskaran
Energy Recovery Circuit Design for Low Power VLSI. iSES (2018)
N. Poornima, V. S. Kanchana Bhaaskaran
Design and Implementation of 32-Bit High Valency Jackson Adders. J. Circuits Syst. Comput. 26 (7) (2017)
Saroja S. Bhusare, V. S. Kanchana Bhaaskaran
Low-Power High-Accuracy Fixed-Width Radix-8 Booth Multiplier Using Probabilistic Estimation Technique. J. Circuits Syst. Comput. 26 (5) (2017)
Kore Sagar Dattatraya, Ritesh Belgudri, Ramdas Bhanudas Khaladkar, V. S. Kanchana Bhaaskaran
Low Power, High Speed and Area Efficient Binary Count Multiplier. J. Circuits Syst. Comput. 25 (4) (2016)
Deeksha Anandani, Anurag Kumar, V. S. Kanchana Bhaaskaran
Gating techniques for 6T SRAM cell using different modes of FinFET. ICACCI (2015)
P. Sasipriya, V. S. Kanchana Bhaaskaran
Two phase sinusoidal power clocked quasi-static adiabatic logic families. IC3 (2015)
Hardik Sangani, Tanay M. Modi, V. S. Kanchana Bhaaskaran
Low power vedic multiplier using energy recovery logic. ICACCI (2014)
M. Divya, Ritesh Belgudri, V. S. Kanchana Bhaaskaran
Design and analysis of program counter using finite state machine and incrementer based logic. ICACCI (2014)
Dalal Rutwik Kishor, V. S. Kanchana Bhaaskaran
Low power divider using vedic mathematics. ICACCI (2014)
V. S. Kanchana Bhaaskaran, J. P. Raina
Pre-Resolve and Sense Adiabatic Logic for 100 kHz to 500 MHz Frequency Classes. J. Circuits Syst. Comput. 21 (5) (2012)
V. S. Kanchana Bhaaskaran, J. P. Raina
Two-Phase sinusoidal Power-Clocked Quasi-Adiabatic Logic Circuits. J. Circuits Syst. Comput. 19 (2) (2010)
V. S. Kanchana Bhaaskaran, J. P. Raina
Differential Cascode Adiabatic Logic Structure for Low Power. J. Low Power Electron. 4 (2) (2008)
V. S. Kanchana Bhaaskaran, S. Salivahanan, D. S. Emmanuel
Semi-Custom Design of Adiabatic Adder Circuits. VLSI Design (2006)